Clocked Inverter Circuit for Low-DCD Data Combining
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Solution Overview
Problem
Semiconductor devices face challenges in combining data at appropriate duty ratios, leading to duty cycle distortion (DCD) due to variations in manufacturing processes, which can result in unsuitable data usage by internal circuits.
Innovation Solution
The semiconductor device generates reversed-phase data and combines it using a comparison circuit to reduce DCD, ensuring the combined data has a duty ratio of about 50%, employing a configuration with clocked inverters and a comparison circuit to synchronize and invert data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data is combined using conventional methods, then the combining process is simple, but duty cycle distortion occurs due to manufacturing variations
Solution Approach 1:
The patent applies inversion by generating reversed-phase data from the input data and using it in the combination process. Specifically, the first input data is inverted to generate first reversed-phase data, and the second input data is inverted to generate second reversed-phase data. These reversed-phase data are then combined with the original data through comparison circuits, which compensates for duty cycle distortion by balancing the effects of manufacturing variations.
Solution Approach 2:
The patent introduces comparison circuits as intermediary elements that combine the original data and reversed-phase data. The first comparison circuit combines first input data and second reversed-phase data, while the second comparison circuit combines second input data and first reversed-phase data. These intermediary comparison circuits act as mediators that balance the duty cycles and eliminate distortion caused by manufacturing variations.
2Manufacturing precision
If reversed-phase data is generated and combined using comparison circuits, then duty cycle distortion is reduced, but the circuit configuration becomes more complex
Solution Approach 1:
The patent merges multiple functions into the comparison circuits, which simultaneously perform data combination and duty cycle balancing. The first comparison circuit merges first input data with second reversed-phase data, while the second comparison circuit merges second input data with first reversed-phase data. This merging approach achieves duty ratio stability while organizing the complexity into functional units.
Solution Approach 2:
The patent changes the phase parameter of the input data by generating reversed-phase versions. By inverting the phase of the data (creating reversed-phase data with 180-degree phase shift), the system transforms the original data parameters to compensate for duty cycle distortion when combined with the original data through comparison circuits.
3Reliability
If conventional data combining is used, then the circuit is simpler, but setup and hold time specifications may not be met
Solution Approach 1:
The patent performs preliminary action by generating reversed-phase data before the final combination step. The first inverter generates first reversed-phase data from first input data, and the second inverter generates second reversed-phase data from second input data. This preliminary inversion prepares the data in advance, ensuring that when the comparison circuits combine the data, the setup and hold time requirements are satisfied due to the balanced duty cycles.
Data Source
AI summary
A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.