Clocked Latch Circuit With Keeper Feedback for Lower Clock Load
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Solution Overview
Problem
Latches and flip-flops in semiconductor devices consume significant switching current due to high clock load, as the clock signal switches twice every cycle, while logic nodes switch much less frequently, leading to inefficiencies in power consumption and reliability concerns from contention issues during data writing and holding modes.
Innovation Solution
A latch circuit design utilizing a feed-forward circuit and feedback circuit with a reduced number of clocked devices, specifically no more than four, to minimize clock load and address contention by employing keeper circuits to maintain logic states during hold modes, thereby reducing switching current and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional latch circuits use multiple clocked devices to ensure proper timing and state holding, then reliability is improved, but switching current consumption increases due to high clock load
Solution Approach 1:
The patent extracts the clock signal dependency from multiple clocked devices and concentrates it into a single clocked device. The feed-forward path uses one clocked device while the feedback path uses transmission gates controlled by clock signals, separating the clocking function from the state holding function and reducing overall clock load.
Solution Approach 2:
The single clocked device in the feed-forward path serves multiple functions: it controls data transmission timing, enables state updates, and works in coordination with the feedback path transmission gates. This multi-functional approach replaces what would traditionally require multiple specialized clocked devices.
2Adaptability or versatility
If the clock signal switches twice every cycle to enable bidirectional control, then operational flexibility is improved, but switching current consumption doubles compared to logic nodes
Solution Approach 1:
The patent uses periodic clock signals to control the transmission gates in the feedback path, enabling bidirectional data flow at different clock phases. The clock signal alternates between phases to enable writing during one phase and reading during another, achieving operational flexibility through time-division multiplexing rather than simultaneous bidirectional control.
Solution Approach 2:
The transmission gates in the feedback path act as intermediaries that are controlled by clock signals. These intermediaries enable bidirectional control functionality without requiring the clock signal itself to switch bidirectionally, reducing the switching burden on the clock distribution network while maintaining operational flexibility.
3Adaptability or versatility
If more clocked devices are used to ensure proper latch operation, then functionality is improved, but device complexity and FET count increase
Solution Approach 1:
The patent merges the clocking control function into a single clocked device in the feed-forward path, while the feedback path uses transmission gates that are clock-controlled but not full clocked devices. This consolidation maintains complete latch functionality (data input, state holding, and output) while reducing the total FET count and device complexity.
Solution Approach 2:
The latch is segmented into a feed-forward path with one clocked device and a feedback path with transmission gates. This segmentation allows each portion to be optimized independently - the clocked device handles timing-critical operations while the transmission gates handle state feedback with lower complexity.
Data Source
AI summary
A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node.