Clocked Latch Circuit Topology for Short-Current and Kickback Control
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Solution Overview
Problem
Latch circuits and sensing amplifiers in existing technologies face issues with short currents during signal transitions and kickback noise, which affect their performance.
Innovation Solution
The proposed solution involves a latch circuit design with additional transistors (M5-M8) that are controlled by a clock signal to prevent short currents, and a sensing amplifier with a comparator circuit and logic circuit that generates control signals using NAND and NOR gates to manage kickback noise without introducing excessive delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional latch circuit design is used, then device complexity is low, but short currents are generated during signal transitions
Solution Approach 1:
The latch circuit is segmented into multiple transistor branches (first branch with M1-M2, second branch with M3-M4, and clock control branch with M5-M8). This segmentation allows independent control of current paths, preventing short currents by ensuring that pull-up and pull-down paths are never simultaneously active. The clock control transistors M5-M8 act as gatekeepers that segment the control signals to current sources based on clock phases.
Solution Approach 2:
Clock control transistors M5-M8 serve as intermediary elements between the clock signal and the current sources. These intermediary transistors translate the clock signal into phased control signals that enable current sources sequentially rather than simultaneously. The intermediaries M5-M8 prevent direct conflict between opposing current paths by mediating the timing of current source activation.
2Reliability
If additional transistors are added to prevent short currents, then reliability improves, but device complexity increases
Solution Approach 1:
The clock control transistors M5-M8 perform multiple functions simultaneously: they control the timing of current sources, prevent short currents by blocking simultaneous activation, and provide clock signal distribution to multiple current sources. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity despite the addition of transistors.
3Object-affected harmful factors
If sensing amplifier uses conventional design, then kickback noise occurs, but circuit simplicity is maintained
Solution Approach 1:
The sensing amplifier incorporates a feedback mechanism where the output of the comparator circuit feeds back to the logic circuit, which in turn controls the latch circuit. This feedback loop allows the system to monitor and adjust its operation to prevent kickback noise. The logic circuit generates control signals based on comparator outputs and clock signals, creating a feedback-controlled system that actively manages noise prevention.
4Reliability
If clock-controlled transistors are used to manage current sources, then short current is prevented, but power consumption increases
Solution Approach 1:
The clock control transistors M5-M8 operate with periodic switching based on clock signals, enabling current sources only during necessary time windows. This periodic action ensures that current sources are active only when needed for signal transitions, rather than continuously, thereby reducing overall power consumption while maintaining reliable current path control during critical operations.
Data Source
AI summary
A first current source and a third current source are coupled at a first output node. A second current source and a fourth current source are coupled at a second output node. Control terminals of a first transistor and a second transistor are coupled to the second output node. Control terminals of a third transistor and a fourth transistor are coupled to the first output node. The first transistor and a fifth transistor are coupled in series between a power terminal and the first output node. A sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal. The third transistor and a seventh transistor are coupled in series between the power terminal and the second output node. An eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal.