Master-Slave Clocked Latch Layout for Low-Delay, Low-Power Storage
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Solution Overview
Problem
Clocked storage elements in digital systems consume significant power and chip area, contributing to increased costs and reduced performance, and existing designs struggle to achieve low insertion delay, small footprint, and low power consumption simultaneously.
Innovation Solution
The design of a compact and fast clocked storage element using a master-slave latch configuration with specific transistor stacks and configurations that eliminate the need for clock signal inversion, reducing insertion delay and power consumption by optimizing transistor paths and layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clocked storage element designs are used, then reliability is maintained, but insertion delay increases and power consumption increases
Solution Approach 1:
The clocked storage element is divided into two separate latches (first latch and second latch) with distinct transistor paths. Each latch handles specific signal transitions, allowing independent optimization of each path for speed and power efficiency.
Solution Approach 2:
Different transistor configurations are used in different parts of the circuit. The first latch uses two p-channel and two n-channel transistors in its current path, while the second latch uses a different arrangement, allowing each section to be optimized for its specific function and reducing overall power consumption while maintaining fast insertion delay.
2Area of stationary object
If conventional clocked storage element designs are used, then functionality is maintained, but chip area increases
Solution Approach 1:
The master latch and slave latch are merged into a single integrated clocked storage element structure. The latches share common supply lines (VDD and VSS) and are closely coupled, reducing the total chip area while maintaining the fast insertion delay performance through optimized internal transistor paths.
3Speed
If clock signal inversion is used in conventional designs, then latch operation is enabled, but insertion delay increases
Solution Approach 1:
The clock inverter stage is extracted and eliminated from the design. Both latches receive the clock signal directly without inversion, removing the delay associated with clock signal conditioning while simplifying the overall circuit structure and reducing the number of required components.
Data Source
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AI summary
A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.