Clocked Latch Circuit Topology for Low-Power High-Speed Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current-mode logic (CML) latch circuits consume higher power due to direct current (DC) power paths compared to complementary metal oxide semiconductor (CMOS) counterparts, which is a challenge in high-speed signal processing applications.
Innovation Solution
A latch circuit design incorporating a switching device that reduces power consumption by limiting the voltage difference between output nodes during a pre-evaluate phase and utilizing amplification circuits to maintain signal integrity while reducing power consumption, achieving performance comparable to CMOS counterparts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-mode logic (CML) latch circuits are used for high-speed signal processing, then operational speed is improved, but power consumption increases due to direct current (DC) power paths
Solution Approach 1:
The patent implements periodic action by using clock signal-controlled switching devices that alternately connect and disconnect power paths to output nodes. The switching devices are turned on during evaluation phases to enable signal processing and turned off during retention phases to block DC current, thereby achieving high-speed operation only when needed while reducing continuous power consumption
Solution Approach 2:
The patent applies dynamics by making the power path connectivity dynamic rather than static. Switching devices controlled by clock signals dynamically adjust the connection between power supply nodes and output nodes, allowing the circuit to transition between high-speed operation mode and low-power retention mode, thus resolving the contradiction between speed and power consumption
2Use of energy by moving object
If switching devices are used to reduce power consumption by limiting voltage difference during pre-evaluate phase, then power consumption decreases, but circuit complexity increases
Solution Approach 1:
The switching devices in the patent serve multiple functions: they control power delivery to output nodes, limit voltage differences during pre-evaluation phases, and enable clock-synchronized operation. By making the switching devices multi-functional, the patent reduces the need for separate dedicated components for each function, thereby managing circuit complexity while achieving power consumption reduction
Data Source
AI summary
A latch circuit includes a first switch between output nodes that toggles responsive to clock signal states, first and second transistors including drains connected directly to the output nodes and gates connected directly and exclusively to input nodes that receive complementary data signals, third and fourth transistors including sources that receive a supply voltage independent of the clock signal, drains connected to the output nodes, and gates connected directly to the output nodes that are connected to a supply node exclusively through the third and fourth transistors, and a node connected exclusively to first and second transistor sources and a second switch connected to a reference node. The data signals vary exclusively between supply and reference voltage levels, and the second switch toggles responsive to the clock signal states such that the output nodes connect to the reference node exclusively through the second and first transistors and the second switch.