Clocked Level Shifter Circuit for Low-Distortion Voltage Conversion

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Solution Overview

Problem

Conventional level shifters experience waveform distortion and duty ratio distortion due to unbalanced pull-up and pull-down times in regulating voltage levels, leading to inefficient operation of electronic devices across different voltage domains.

Innovation Solution

The proposed electronic device incorporates a level shifter with a level shifting circuit, first and second adjusting circuits, and specific transistors (PMOS and NMOS) that dynamically control current flow based on voltage levels and clock signals to quickly adjust output voltage, reducing unbalance and distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional level shifter is used to convert voltage levels, then the voltage level conversion is achieved, but waveform distortion and duty ratio distortion occur due to unbalanced pull-up and pull-down times

Engineering Contradiction:
Improvevoltage level conversion accuracyVSAvoidwaveform distortion
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by configuring different transistor arrangements for pull-up and pull-down paths. Specifically, the first transistor (PMOS) and second transistor (NMOS) are configured with different characteristics and connection topologies to compensate for the inherent asymmetry in PMOS and NMOS transistor performance, thereby balancing the pull-up and pull-down times and reducing waveform distortion

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes transistor parameters by selecting transistors with specific threshold voltages, channel widths, and lengths to optimize the pull-up and pull-down speeds. The first and second transistors are configured with different parameters to achieve balanced charging and discharging times, which reduces duty ratio distortion while maintaining accurate voltage level conversion

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the level shifter uses standard transistor configuration, then the circuit complexity is low, but the pull-up and pull-down times are unbalanced causing duty ratio distortion

Engineering Contradiction:
Improvecircuit structure simplicityVSAvoidduty ratio accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent implements dynamic balancing by using clock signal-controlled switching transistors that adaptively adjust the pull-up and pull-down paths based on the input signal state. The third and fourth transistors are controlled by clock signals to dynamically enable or disable specific current paths, achieving balanced transition times without requiring a permanently complex circuit structure

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables faster pull-up and pull-down of output voltages, minimizing waveform and duty ratio distortion, ensuring stable operation across different voltage domains.

Implementation Method 1

The first PMOS transistor may determine whether to connect a supply voltage line with a second node, based on a voltage level of a first node

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

The second PMOS transistor may determine whether to connect the second node with a third node, based on a clock signal swinging between a first voltage level and a second voltage level

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

The first NMOS transistor may determine whether to connect the third node with a ground voltage line, based on the clock signal

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 4

The third PMOS transistor may determine whether to connect the supply voltage line with an output node, based on a voltage level of the third node

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 5

The second NMOS transistor may determine whether to connect the first node with a ground voltage line, based on an inverted clock signal, a phase of the inverted clock signal corresponding to an inverted version of a phase of the clock signal

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11159149B2Electronic device including level shifter
Publication Date: 2021.10.26 SAMSUNG ELECTRONICS CO LTD
  • US11159149B2 patent drawing
  • US11159149B2 patent drawing
  • US11159149B2 patent drawing

AI summary

Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.