Clocked Level Shifter With Differential Sensing for SRAM Voltage Splits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional level shifters face limitations in supply voltage split range, which restricts the voltage range compatibility between low voltage domains used for power conservation and high voltage domains required for performance enhancement in devices like SRAM, leading to increased memory access time and power consumption.
Innovation Solution
Incorporating a differential sensing transistor pair that allows for a larger supply voltage split range by shifting input signals from a low voltage domain (VDD) to a higher voltage domain (VDDM), enabling efficient operation and minimizing power consumption through complementary output signals and an enable circuit that equalizes voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional level shifters are used to shift voltage levels, then voltage level shifting is achieved, but the supply voltage split range is limited
Solution Approach 1:
The patent changes the electrical parameters of the level shifter by introducing a differential sensing transistor pair that operates with complementary output signals. This allows the circuit to handle a wider supply voltage split range by dynamically adjusting the voltage levels at different operating points, thereby expanding the adaptable voltage range while maintaining reliable signal transmission.
Solution Approach 2:
The differential sensing transistor pair acts as an intermediary mechanism between the low voltage domain and high voltage domain. It mediates the voltage level shifting process by using two transistors working in differential mode, which enables broader voltage compatibility while maintaining signal integrity across the voltage domain boundary.
2Speed
If voltage level shifting is performed with limited supply voltage split range, then device operation is maintained, but memory access time increases
Solution Approach 1:
By changing the operational parameters of the level shifter through differential sensing transistors, the patent enables faster voltage level transitions. The complementary output signals allow for more rapid switching between voltage domains, directly improving memory access speed by reducing the time required for voltage level conversion during read/write operations.
3Use of energy by moving object
If voltage level shifting is performed with limited supply voltage split range, then device operation is maintained, but power consumption increases
Solution Approach 1:
The patent optimizes power consumption by changing the voltage operating parameters dynamically. The differential sensing transistor pair enables the circuit to operate efficiently across a broader voltage range by adjusting the voltage levels according to the specific operating conditions, thereby reducing unnecessary power dissipation while maintaining voltage range compatibility.
Solution Approach 2:
The level shifter circuit serves itself by using complementary output signals that automatically adjust the voltage levels based on the input signal state. This self-regulating mechanism reduces the need for external voltage regulation circuitry, lowering overall power consumption while maintaining adaptability across different voltage ranges.
Data Source
AI summary
A level shifter includes: a first inverter configured to receive an input signal in a first voltage domain and shift the input signal from the first voltage domain to a first output signal at a first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of a first clock signal in the first voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the first voltage domain to a second output signal at a second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.