Multiplexing Latch Circuit with Integrated Clocking for On-Chip Testing
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Solution Overview
Problem
In integrated circuits, especially at small process nodes, wafer probes are fragile and less favorable, leading to a need for on-chip testing, which is challenging due to the inability to test individual devices like memory or processors effectively during or after manufacture.
Innovation Solution
An interface circuit with a clock generator and multiplexing latch circuit that generates latching clock signals to select and latch data, reducing the number of transistors and switching delays, thereby increasing speed and reducing space, allowing for efficient on-chip testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a separate multiplexer and latch are used for on-chip testing, then data selection and latching functions are achieved, but the number of transistors increases and circuit speed decreases due to multiple switching delays
Solution Approach 1:
The patent combines the multiplexer and latch into a single integrated circuit block that performs both data selection and latching functions simultaneously. This merging eliminates the need for separate multiplexer and latch components, reducing the total transistor count and eliminating intermediate switching delays between stages, thereby improving circuit speed while maintaining full functionality
Solution Approach 2:
The integrated circuit is designed to perform multiple functions - both multiplexing (data selection) and latching (data storage) - within a single device. This multi-functional approach allows the circuit to replace what would traditionally require separate dedicated components, reducing overall device complexity and improving signal transmission speed by eliminating inter-component delays
2Area of stationary object
If a separate multiplexer and latch are used, then complete data selection and latching functionality is provided, but the space occupied in the integrated circuit increases
Solution Approach 1:
The patent merges the multiplexer and latch into a single integrated circuit block, which significantly reduces the area occupied in the integrated circuit layout. By consolidating two separate components into one, the physical space required is reduced while maintaining all necessary functionality for data selection and latching operations
3Speed
If multiple switching stages are used for data selection and latching, then complete operational functionality is achieved, but switching delays increase and reduce circuit speed
Solution Approach 1:
The patent combines the multiplexer and latch into a single integrated circuit block, which significantly reduces the area occupied in the integrated circuit layout. By consolidating two separate components into one, the physical space required is reduced while maintaining all necessary functionality for data selection and latching operations
Data Source
AI summary
A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value. A multiplexing latch circuit is configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.