Clocked Parity Check Circuit for Glitch-Free XOR Timing
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Solution Overview
Problem
Existing parity check circuits face issues with asynchronous delay, leading to data errors and difficulties in accurately setting parity operation timing, especially when performing XOR combinations on multiple bits, which can result in increased circuit complexity and errors.
Innovation Solution
A parity check circuit design that includes a signal combination unit for generating combination signals, a parity check unit for error detection, and a signal storage unit for reconstructing data, all operating in synchronization with a clock to minimize asynchronous delay and prevent circuit complexity increases by using flip-flops between combination stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-stage XOR gates are used to generate parity data for multiple data bits, then parity check capability is improved, but asynchronous delay increases causing data errors and timing difficulties
Solution Approach 1:
The patent divides the multi-bit data into multiple groups, with each group processed by a separate XOR gate to generate individual parity bits. This segmentation reduces the propagation delay compared to processing all bits through a single multi-stage XOR gate, as each XOR gate operates independently on a smaller subset of bits.
Solution Approach 2:
The patent introduces a clock signal that operates periodically to control the timing of parity check operations. The clock signal synchronizes the latching of data bits and the generation of parity bits, ensuring that all operations occur at predetermined timing intervals, thereby eliminating asynchronous delay issues.
2Reliability
If multi-stage XOR gates are used to generate parity data, then parity check capability is improved, but timing accuracy deteriorates
Solution Approach 1:
The patent uses a clock signal with predetermined periodicity to control when data bits are latched and when parity bits are generated. This periodic timing ensures that all XOR operations start and complete at known, consistent times, providing accurate and predictable timing for the parity check operation.
Solution Approach 2:
The patent uses the clock signal as a feedback mechanism to synchronize all operations. The clock signal ensures that data bits are latched at the same time and that parity bits are generated based on synchronized inputs, thereby maintaining accurate timing relationships throughout the circuit.
3Measurement precision
If additional circuits are added to fix asynchronous delay issues, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines the timing control function with the existing XOR gate structure by using a shared clock signal that controls both the data latching and the parity generation. This merging approach avoids adding separate, complex timing control circuits while still achieving accurate timing synchronization.
Data Source
AI summary
A parity check circuit may include a first signal combination unit for generating first to Nth combination signals by combining first to Nth signals, wherein a Kth (K is a natural number of 2≤K≤N) combination signal of the first to Nth combination signals is obtained by combining the first to Kth signals of the first to Nth signals, a parity check unit for detecting whether an error is present in the first to Nth signals in response to the Nth combination signal, a second signal combination unit for generating first to Nth reconstruction signals by combining the first to Nth combination signals, wherein a Kth reconstruction signal of the first to Nth reconstruction signals is obtained by combining a (K−1)th combination signal and the Kth combination signal of the first to Nth combination signals, and a signal storage unit for storing the first to Nth reconstruction signals.