Clocked Ports for Processor Interface Timing
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Solution Overview
Problem
Processor designers face challenges in efficiently handling multiple external devices due to the limitations of existing interrupt handling and polling methods, which are either complex and costly or energy-inefficient, particularly in mobile applications where configurability, speed, and power consumption are critical.
Innovation Solution
A processor with an interface portion and internal environment, featuring an execution unit and thread scheduler that separates the timing of thread scheduling from the timing of interface operations, allowing for independent scheduling of threads and improved reaction time to external stimuli, using a dual timing signal system to manage data transfer and ready signals across ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt handling is used to manage external devices, then the processor can respond to external stimuli, but the system complexity and cost increase
Solution Approach 1:
The patent extracts the timing function from the main processor by introducing a separate clock signal for the port. This allows the port to operate independently with its own timing, removing the burden of timing management from the processor's interrupt handling logic and reducing overall system complexity while maintaining reliable external device communication
Solution Approach 2:
The patent introduces a ready signal as an intermediary between the port and the processor. This ready signal acts as a mediator that coordinates data transfer timing without requiring complex interrupt handling, simplifying the interaction between external devices and the processor while ensuring reliable communication
2Ease of operation
If polling is used to check device readiness, then the processor can maintain control, but energy consumption increases
Solution Approach 1:
The patent replaces continuous polling with periodic action driven by a dedicated clock signal. The port is clocked independently at appropriate intervals, allowing the processor to maintain control through the ready signal mechanism while consuming significantly less energy compared to continuous polling operations
Solution Approach 2:
The port performs self-service by using its own clock signal to manage data transfer timing and generate ready signals autonomously. This eliminates the need for the processor to continuously poll devices, reducing energy consumption while the processor retains control through event-driven ready signal response
3Adaptability or versatility
If FPGAs are used for interface controllers, then configurability is achieved, but cost and power consumption increase
Solution Approach 1:
The patent segments the interface controller functionality by separating the clocking mechanism from the processor core. The independent port clock can be configured for different timing requirements while the processor remains unchanged, achieving configurability through modular timing control rather than requiring full FPGA implementation, thus reducing power consumption
Solution Approach 2:
The patent achieves configurability by changing the timing parameters through the independent port clock signal. Different clock frequencies and phases can be configured for different ports to match various external device requirements, providing FPGA-like adaptability in a standard processor architecture with lower power consumption
4Device complexity
If multiple ports are serviced sequentially by the execution unit, then timing is simplified, but reaction time to external stimuli increases
Solution Approach 1:
The patent implements preliminary action by having ports generate ready signals in advance when they are prepared for data transfer. The thread scheduler can then proactively schedule threads based on these advance notifications, reducing reaction time while the execution unit maintains its sequential servicing approach with simplified timing
Data Source
Figure 1
Figure 2
Figure 2A
AI summary
A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.