Clocked Receiver I/O Sensor for Die-to-Die Link Degradation Detection
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Solution Overview
Problem
Current die-to-die connectivity monitoring technologies face challenges in accurately assessing the quality of high-speed interconnects between integrated circuits (ICs) without disrupting normal operation and are limited in detecting degradation over time.
Innovation Solution
The implementation of an I/O sensor system that uses a programmable delay line and a clocked receiver to compare data signals, allowing for the estimation of connectivity quality by measuring eye pattern parameters such as eye width and height, while operating in parallel with the interconnect lane and scanning for changes in signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional connectivity monitoring methods are used, then connectivity quality can be assessed, but normal operation is disrupted and degradation detection is limited
Solution Approach 1:
The monitoring function is segmented into a separate I/O sensor module that operates independently from the main interconnect lane. The sensor includes its own delayed sampling device, comparison circuit, and controller, allowing it to monitor connectivity quality without disrupting the primary data transmission path between ICs.
Solution Approach 2:
An I/O sensor acts as an intermediary component between the transmitter and receiver ICs. It taps into the interconnect lane to sample data signals and uses a programmable delay line to create delayed versions of these signals for comparison, enabling continuous monitoring without becoming a bottleneck or disruption point in the data path.
2Speed
If high-speed data transmission is maintained, then data transmission rate is high, but timing precision for monitoring degrades
Solution Approach 1:
The system employs a dynamic, programmable delay line that can be adjusted in real-time to optimize the timing of sampled signals. The controller gradually adjusts the delay amount and uses multiple delay settings to scan for the optimal sampling point, allowing the monitoring system to adapt to varying data transmission rates and maintain precise timing measurements even at high speeds.
Solution Approach 2:
The system performs preliminary scanning operations to identify optimal sampling timing points before actual monitoring begins. The controller systematically varies the delay parameter to detect transitions in comparison results, establishing reference timing information that enables precise monitoring during high-speed operation without requiring complex real-time adjustments.
3Reliability
If continuous monitoring is implemented, then degradation detection is improved, but power consumption increases
Solution Approach 1:
The monitoring system operates periodically rather than continuously at full capacity. The controller implements scanning operations where it gradually adjusts the delay parameter in steps, performs comparisons at each delay setting, and detects transitions in comparison results. This periodic scanning approach enables effective degradation detection while consuming significantly less power than continuous full-rate monitoring would require.
Data Source
AI summary
An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.