Clocked Reference Buffer for Stable High-Throughput SAR ADCs
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Solution Overview
Problem
Noise and glitches in reference voltages and bias currents can adversely affect the operation of analog-to-digital converter (ADC) circuits, leading to errors in comparator outputs, and existing solutions often require delay circuitry to ensure stability, which can limit ADC throughput.
Innovation Solution
A clocked reference buffer is implemented, using a transistor and capacitor configuration with a switch to sample and isolate the reference voltage during ADC conversion phases, allowing charge stored on the capacitor to bias the transistor and provide a regulated voltage, thereby suppressing noise and improving power supply rejection ratio without adding noise to the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If delay circuitry is added to allow reference voltage to settle, then stability of reference voltage is improved, but ADC throughput rate deteriorates
Solution Approach 1:
The reference voltage is settled and stabilized in advance during a precharge phase before the actual conversion operation begins. The capacitor is precharged to the reference voltage level, so when conversion starts, the stable voltage is already available immediately without requiring delay circuitry during the critical conversion period.
Solution Approach 2:
The circuit operates in periodic phases including a precharge phase where the capacitor is charged to reference voltage, followed by a conversion phase where the stored charge is used. This periodic switching between charging and using the reference voltage allows the system to maintain high throughput while ensuring stability during conversion operations.
2Reliability
If delay circuitry is added to allow bias current to settle, then operation reliability is improved, but settle time increases
Solution Approach 1:
The bias current is settled and stabilized in advance during the precharge phase before conversion begins. By preparing the bias current in advance, the circuit ensures reliable operation during conversion without requiring additional settle time that would increase overall operation duration.
3Object-affected harmful factors
If switch is used to decouple capacitor during conversion phase, then noise suppression is improved, but circuit complexity increases
Solution Approach 1:
The switch extracts and removes the capacitor from the active circuit path during the conversion phase by opening the connection. This isolation technique suppresses noise by taking out the potentially noisy capacitor element from the signal path while maintaining simplicity through a single switching action rather than complex filtering or shielding circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high-speed settling and high-accuracy in ADC operations, enabling a high ADC throughput rate with improved common-mode rejection and expanded single-ended mode, reducing settle-time induced delays and enhancing the stability of reference voltages.
Implementation Method 1
a capacitor coupled to the gate and a switch configured to selectively provide a voltage to the capacitor during a first phase of an analog-to-digital converter (ADC) conversion operation and to decouple the voltage from the capacitor during a second phase of the ADC conversion operation
Data Source
AI summary
A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.