Clocked RS Latch Circuit With Reduced Inversion Delay
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Solution Overview
Problem
High-frequency circuit designs face latency issues due to the delays in latches and registers, making it difficult to pipeline signals effectively, especially when converting dual-rail clocked signals to static signals for use in static logic gates.
Innovation Solution
A clocked RS latch circuit design with a first stage comprising a latch node between pull-up and pull-down devices, and a second stage with additional pull-up and pull-down devices directly coupled to the first stage, along with an output inverter and hold circuitry to minimize latency by reducing the number of transistors and signal inversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional AOI-based clocked RS latch circuit is used to convert clocked signals to static signals, then signal conversion function is achieved, but latency is relatively long due to multiple transistors and signal inversions
Solution Approach 1:
The patent extracts and removes unnecessary signal inversion stages from the conventional AOI-based latch circuit. By using a simplified CMOS latch structure with direct pull-up and pull-down transistors controlled by clock and data signals, the design eliminates redundant inverting operations while maintaining the clocked-to-static signal conversion function, thereby reducing latency.
Solution Approach 2:
The latch circuit is segmented into distinct functional blocks: clock control transistors, data control transistors, pull-up network, and pull-down network. This segmentation allows each component to perform its specific function efficiently without the signal having to traverse through multiple complex gate structures, reducing overall propagation delay.
2Productivity
If more levels of latching are added to pipeline signals through stages, then signal passing through pipeline is achieved, but delay from latches and registers becomes a large fraction of clock cycle
Solution Approach 1:
The patent changes the operational parameters of the latch circuit by using optimized transistor sizing and a simplified CMOS structure that reduces propagation delay. This allows the latch to operate faster, making the latch delay a smaller fraction of the clock cycle and enabling more pipeline stages to be effectively utilized.
3Reliability
If D-type latch is used instead of AOI-based RS latch, then alignment issues with clock edges may cause false transitions, but structure is simpler
Solution Approach 1:
The patent incorporates feedback mechanisms through cross-coupled transistors that maintain the latched state. The output of the latch is fed back to the control nodes, ensuring that once a state is captured, it is maintained reliably until the next clock cycle, preventing false transitions while using a structured CMOS design.
Data Source
AI summary
An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device (418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420). The clocked latch circuit is operable to pull the latch node (420) low under at least one logical combination of the inputs, and pull the latch node high under at least one other logical combination of the inputs.