Clocked SPAD Quench and DRAM Gain Cell Memory for dToF Pixels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-of-flight lidar systems face inefficiencies in memory usage due to high transistors per memory cell, bit depth, and number of histogram bins, leading to increased surface area and power requirements, particularly in direct time of flight measurements using Single Photon Avalanche Diodes (SPADs).
Innovation Solution
The implementation of a LIDAR system with a control circuit that includes a photodetector control circuit for quenching and resetting SPADs using a global clock signal and a memory control circuit for incrementing data in DRAM-based memory cells, utilizing charge sharing between memory cells to reduce bit line capacitance and eliminate delay logic, allowing for efficient memory access and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory structures (SRAM with 6 transistors per bit) are used in ToF pixels, then memory storage capacity is improved, but transistor count and surface area per pixel increase significantly
Solution Approach 1:
The patent extracts the memory function from conventional SRAM structures and implements it using DRAM cells with only 2 transistors per bit. This extraction of the essential memory storage function while removing unnecessary circuit components (reducing from 6 to 2 transistors per bit) directly resolves the contradiction by maintaining storage capacity while dramatically reducing pixel surface area
Solution Approach 2:
The patent changes the fundamental parameter of transistor count per memory bit from 6 (SRAM) to 2 (DRAM), representing a 66% reduction. This parameter change enables the same memory storage capacity to be achieved with significantly fewer transistors and smaller surface area per pixel
2Extent of automation
If conventional counters (D-type or T-type flip-flops with around 32 transistors) are used for photon counting, then counting capability is improved, but transistor count and power consumption increase
Solution Approach 1:
The patent extracts the essential counting function from complex 32-transistor flip-flop counters and implements it using simple DRAM cell charge sharing mechanisms. By taking out only the essential counting capability and removing unnecessary counter logic, the system achieves photon counting with dramatically reduced transistor count and device complexity
Solution Approach 2:
The patent replaces the mechanical/electronic counter system (flip-flops with 32 transistors) with an electrical charge-based counting system using DRAM cells. This substitution eliminates complex transistor switching mechanisms and uses simple charge accumulation and sharing, reducing device complexity while maintaining counting capability
3Measurement precision
If histogramming memory with high bit depth and many bins is implemented, then measurement precision is improved, but memory resources and power requirements increase
Solution Approach 1:
The patent changes the memory architecture from high-bit-depth SRAM to low-bit-depth DRAM with charge-based storage. By changing the fundamental parameter of how data is stored (from voltage levels requiring high bit depth to charge accumulation), the system achieves the same measurement precision with reduced memory resources and lower power consumption
Solution Approach 2:
The patent uses charge sharing between DRAM cells as a copy mechanism for incrementing histogram bins. Instead of using complex write logic, the system copies charge between cells to increment counts, reducing power consumption while maintaining measurement precision
4Measurement precision
If active quench circuits with delay logic are used for SPAD reset, then timing control is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the essential quench function from complex active quench circuits with delay logic and implements it using simple DRAM cell reset mechanisms. By taking out only the essential quench capability and removing unnecessary delay logic and control circuits, the system achieves precise timing control with dramatically reduced device complexity
Solution Approach 2:
The patent implements self-service quenching where the DRAM cell structure itself provides the timing control functionality. The intrinsic properties of the DRAM cell (capacitance discharge and recharge) provide the necessary timing control without external delay logic, reducing device complexity while maintaining precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables compact, low-power, and efficient memory operations in LIDAR systems, reducing power consumption and increasing the potential for sub-10 micrometer pitch dToF pixels, while maintaining high sensitivity and timing resolution.
Implementation Method 1
The high reverse bias voltage generates a sufficient magnitude of electric field such that a single charge carrier introduced into the depletion layer of the device can cause a self-sustaining avalanche via impact ionization
Implementation Method 2
A SPAD is based on a semiconductor junction (e.g., a p-n junction) that may detect incident photons when biased beyond its breakdown region
Implementation Method 3
The initiating charge carrier can be photo-electrically generated by a single incident photon striking the high field region
Implementation Method 4
The avalanche is quenched by a quench circuit, either actively (e.g., by reducing the bias voltage) or passively (e.g., by using the voltage drop across a serially connected resistor), to allow the photodetector to be recharged
Implementation Method 5
utilizing charge sharing between memory cells to reduce bit line capacitance
Data Source
AI summary
A Light Detection and Ranging (LIDAR) detector circuit includes one or more photodetector elements configured to output respective detection signals indicating respective detection events responsive to light incident thereon, and at least one control circuit. The at least one control circuit is configured to receive the respective detection signals from the one or more photodetector elements, and to reset the one or more photodetector elements responsive to a transition of a clock signal after the respective detection events. Related memory devices and systems are also discussed.