Clocked Storage Element Layout for Low-Delay, Low-Power Latching
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Solution Overview
Problem
Clocked storage elements in digital systems consume significant power and chip area, contributing to increased costs and reduced performance, and existing designs struggle to achieve low insertion delay and compact size while maintaining low power consumption.
Innovation Solution
The design of compact and fast clocked storage elements using a configuration of latches with specific transistor paths and configurations that eliminate the need for clock signal inversion, reducing insertion delay and power consumption by optimizing transistor stacks and layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional clocked storage element designs are used, then reliability is maintained, but insertion delay increases and power consumption increases
Solution Approach 1:
The clocked storage element is divided into two separate latches (first latch and second latch) with distinct transistor paths. Each latch handles specific signal paths independently, allowing optimization of each segment's transistor configuration to minimize overall insertion delay while maintaining functionality.
Solution Approach 2:
The patent introduces a novel transistor stacking arrangement that utilizes vertical stacking of transistors (p-channel over n-channel) to create compact current paths. This dimensional reorganization reduces the horizontal space required and optimizes signal propagation paths, achieving lower insertion delay without proportionally increasing device area.
2Speed
If more transistors are added to reduce insertion delay, then speed improves, but device area increases
Solution Approach 1:
The patent employs vertical transistor stacking where p-channel transistors are stacked over n-channel transistors, utilizing the vertical dimension to reduce horizontal footprint. This stacking approach achieves fast signal propagation (low insertion delay) while minimizing the area occupied by the clocked storage element on the chip.
Solution Approach 2:
The first and second latches are integrated into a unified clocked storage element structure where shared components and coordinated transistor paths reduce overall area. The merging of functionality into a compact unit achieves high speed performance without proportionally increasing chip area.
3Ease of operation
If clock signal inversion is implemented, then latch control is improved, but insertion delay increases due to inverter settling time
Solution Approach 1:
The patent extracts and eliminates the clock inverter from the critical signal path by using separate clock input nodes for the first and second latches. Each latch receives clock signals directly without requiring inversion, removing the inverter settling time delay from the insertion delay measurement while maintaining proper latch control through differential clock phase management.
4Area of moving object
If compact transistor stacking is used, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The vertical stacking of transistors utilizes the vertical dimension to achieve compact area footprint. While this increases manufacturing precision requirements for vertical alignment, the standardized CMOS fabrication processes and careful device layout design mitigate these challenges, achieving area reduction with acceptable manufacturing tolerances.
Data Source
AI summary
A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.