Clock-Synchronized Time-Encoding Modulator for Low-Power ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional time-encoding modulators used in ADC circuits face high power consumption due to the need for high-frequency VCOs, which is a challenge especially for battery-powered devices requiring continuous operation for voice control and force sensing applications.
Innovation Solution
A time-encoding modulator design that synchronizes transitions in the time-encoded signal to a clock signal, using a hysteretic comparator module and loop filter to generate a PWM signal, allowing for low power operation by introducing quantization error within the modulator loop and reducing noise shaping, while maintaining accurate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a VCO operates at relatively high frequencies to provide acceptable noise performance, then noise performance is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating parameters of the VCO by synchronizing it to a clock signal and allowing it to operate at lower frequencies while maintaining noise performance through synchronized transition timing. The hysteretic comparator module generates transitions synchronized to clock edges, enabling the VCO to run at reduced frequencies without sacrificing noise performance, thus resolving the contradiction between noise performance and power consumption.
2Reliability
If continuous operation is implemented for voice control and force sensing applications, then detection capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action through clock-synchronized transitions in the time-encoded signal. By synchronizing VCO transitions to clock edges, the system creates a periodic operation pattern that maintains detection capability while enabling power management. The synchronized timing allows the system to operate continuously when needed while providing a structured framework for reducing power consumption during idle periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption while maintaining accurate signal conversion, enabling efficient operation in low-power devices such as voice-controlled and force-sensing applications by synchronizing transitions and applying noise shaping within the modulator loop.
Implementation Method 1
a hysteretic comparator module in the feedforward path configured to generate the time encoded signal at a first node based on the input signal and a feedback signal
Implementation Method 2
a loop filter configured to apply filtering to one of: the feedback path; or the feedforward path upstream of the hysteretic comparator module
Data Source
AI summary
This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK1).