Clocking Methodology for At-Speed Scan Testing of Cross-Domain Paths
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Solution Overview
Problem
Existing methods for at-speed testing of cross-domain paths in integrated circuits with synchronous clock domains fail to effectively test for delay defects at the period of the higher-frequency clock, especially when using launch-on-capture methodology, and often result in high sequential depth and low coverage of delay defects.
Innovation Solution
A clocking method that selectively aligns capture or launch edges of clock domains to test cross-domain paths for a propagation time equal to the period of the higher-frequency clock, minimizing sequential depth by disabling unnecessary capture operations and using dual clock alignments to detect delay defects in both launch-on-shift and launch-on-capture methodologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the period of the lower-frequency clock is used for testing cross-domain paths, then the circuit analysis is simplified and fair coverage of delay defects is achieved, but it is impossible to test for propagation time equal to the period of the higher-frequency clock
Solution Approach 1:
The patent applies dynamics by making the clock alignment configuration adaptable and changeable. The testing system can dynamically switch between aligning capture edges and aligning launch edges based on the specific testing requirements. This dynamic configuration allows the same basic methodology to serve multiple testing scenarios (testing for lower-frequency clock period and testing for higher-frequency clock period) without requiring separate fixed methodologies for each case.
2Measurement precision
If other known methods are used to test for cross-domain path propagation times equal to the period of the highest frequency clock, then higher frequency testing is achieved, but the sequential depth of the circuit becomes large and the coverage of delay defects is relatively low
Solution Approach 1:
The patent applies local quality by selectively enabling or disabling capture operations in specific clock domains based on the testing objective. When testing for higher-frequency clock period, the methodology enables capture in the destination domain only when necessary (when the path crosses from lower to higher frequency domain), rather than universally enabling all captures. This localized approach to capture enabling minimizes the sequential depth in the analyzed circuit while maintaining the ability to test high-frequency paths.
Solution Approach 2:
The patent segments the testing methodology into two distinct approaches: aligning capture edges for testing paths from higher to lower frequency domains, and aligning launch edges for testing paths from lower to higher frequency domains. This segmentation allows the testing system to handle different cross-domain path scenarios with appropriate specialized techniques, reducing the overall circuit sequential depth required for analysis while achieving comprehensive coverage.
3Measurement precision
If other known methods are used to test for cross-domain path propagation times equal to the period of the highest frequency clock, then higher frequency testing is achieved, but the circuit analysis time for fault simulation and test generation becomes prohibitive
Solution Approach 1:
The patent reduces circuit analysis time by applying local quality - selectively enabling capture operations only in specific clock domains and scenarios where they are necessary. When testing cross-domain paths, the methodology determines whether capture is needed in the destination domain based on the specific path being tested and the frequency relationship between source and destination domains. This selective approach minimizes the sequential depth that needs to be analyzed, thereby reducing fault simulation and test generation time.
4Reliability
If launch-on-capture methodology is used for testing cross-domain paths, then delay defect detection is enabled, but the sequential depth of the circuit increases and defect coverage remains low
Solution Approach 1:
The patent applies dynamics by making the capture enablement configurable and adaptable to the specific testing scenario. Rather than universally enabling capture in all domains (which increases sequential depth), the system dynamically determines which captures are necessary based on the cross-domain path being tested. This dynamic configuration maintains delay defect detection capability while minimizing the sequential depth increase associated with launch-on-capture methodology.
Solution Approach 2:
The patent applies local quality by selectively enabling capture operations in specific clock domains based on the testing objective. When using launch-on-capture methodology for cross-domain testing, the system enables capture only in the destination domain when the path requires it (such as when testing from lower to higher frequency domain), rather than enabling all captures universally. This localized capture approach maintains reliability for delay defect detection while minimizing the sequential depth increase.
Data Source
AI summary
A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.