Automated Clocking System for Digital Circuit Timing Skew
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Solution Overview
Problem
Conventional automated circuit design tools fail to effectively address inherent clock signal skew in digital circuits, particularly in high-speed designs with clock gaters, leading to critical timing issues that hinder automatic synthesis.
Innovation Solution
An automated digital circuit design tool that includes a clock signal generator, control logic, and clock gaters, which allows for early clock signals to be provided to registers, reducing adverse timing constraints by adjusting clock signal delays through a buffered clock tree, enabling increased clock frequency while meeting timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If conventional automated circuit design tools are used to design digital circuits with clock gaters, then the circuit can be automatically synthesized, but inherent clock signal skew occurs that creates critical timing paths and prevents automatic synthesis in high-speed circuits
Solution Approach 1:
The patent applies preliminary action by providing early clock signals to control logic registers before the main clock signal arrives at other registers. The design tool automatically identifies registers that drive clock gaters and routes early clock signals to them, allowing these registers to be ready earlier and eliminating the critical timing path created by clock signal skew. This preliminary timing adjustment enables automatic synthesis while satisfying timing constraints.
2Use of energy by moving object
If clock gaters are placed between clock source and registers to conserve power and reduce heat generation, then power consumption is reduced, but clock insertion delay increases creating adverse timing constraints
Solution Approach 1:
The patent resolves this contradiction by providing early clock signals to registers that drive clock gaters before the delayed clock signal arrives from the clock tree. This preliminary action compensates for the time loss introduced by clock gaters, allowing the circuit to maintain power-saving benefits while meeting timing constraints through automated timing adjustment.
Solution Approach 2:
The design tool automatically adjusts timing parameters by identifying critical paths through clock gaters and modifying clock signal distribution timing. It changes the effective clock arrival time at specific registers by routing early clock signals, thereby compensating for insertion delays while maintaining the power-saving function of clock gaters.
3Reliability
If the clock tree is buffered to restore clock signal strength for driving multiple registers, then signal integrity is improved, but clock insertion delay increases proportionally to routing delay
Solution Approach 1:
The patent applies preliminary action by routing early clock signals directly to registers that drive clock gaters, bypassing the delayed path through the buffered clock tree. This allows the registers to receive clock signals earlier, compensating for the time loss introduced by buffering and routing delays in the main clock tree while maintaining signal integrity.
4Productivity
If the clock period is reduced to increase clock frequency for high-speed operation, then circuit performance is improved, but the clock period becomes smaller than the clock insertion time making timing constraints impossible to meet
Solution Approach 1:
The patent enables high clock frequencies by providing early clock signals to critical registers before the main clock signal arrives. This preliminary timing adjustment effectively reduces the required clock period by creating timing headroom, allowing the circuit to operate at higher frequencies while still meeting setup and hold time constraints despite clock insertion delays.
Data Source
AI summary
The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.