Clockless Multi-Stage ADC for Low-Power 12-Bit Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving low power dissipation, small area occupation, high sampling rate capability, and 12-bit resolution while minimizing clock requirements, particularly in multi-channel applications such as radiation detection systems.
Innovation Solution
A clockless analog-to-digital converter design comprising two sections with n cells each, utilizing current sinks and inverters to perform analog-to-digital conversion, along with a transient absorbing circuit and sample and hold circuit to manage current and voltage efficiently, allowing for a 12-bit resolution with reduced power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADC topologies (Pipeline or SAR) are used to achieve 12-bit resolution at a few Msps sampling rate, then the required resolution and sampling rate are met, but power consumption increases to 10-42 mW
Solution Approach 1:
The ADC is divided into multiple stages with different resolutions. The first stage performs coarse conversion with lower resolution, and the second stage performs fine conversion with higher resolution. This segmentation allows each stage to operate at optimized power levels, achieving overall 12-bit resolution without requiring the entire system to consume high power continuously.
Solution Approach 2:
The ADC operates in periodic phases including sampling phase, holding phase, and conversion phase. During the sampling phase, the sample and hold circuit captures the input signal. During the holding phase, the signal is maintained at a stable voltage. During the conversion phase, the clocked operation performs the actual digitization. This periodic operation allows the circuit to be powered down or operated at lower power between active conversion cycles.
2Measurement precision
If SAR ADC with N clock cycles is used to achieve N-bit resolution, then the resolution requirement is met, but the clock frequency requirement increases and area occupation increases to 1.1 mm2
Solution Approach 1:
The 12-bit resolution is achieved through two separate conversion stages rather than a single SAR ADC. The first stage handles the most significant bits and the second stage handles the least significant bits. This segmentation reduces the complexity and area of each individual stage compared to a full 12-bit SAR ADC, while achieving the same overall resolution.
Solution Approach 2:
The second stage ADC is effectively nested within the overall conversion process, taking the residual error from the first stage as its input. This nested structure allows the system to achieve high overall resolution by combining the outputs of two lower-resolution converters, reducing the total area required compared to a single high-resolution converter.
3Productivity
If high sampling rate of a few Msps is implemented, then the sampling rate requirement is met, but the clock frequency requirement increases and power consumption increases
Solution Approach 1:
The ADC uses periodic clocked operation where the sampling, holding, and conversion occur in distinct phases. The clock signal enables the switches and latches to operate synchronously only during the conversion phase, rather than continuously. This periodic action allows the circuit to support high sampling rates while consuming power only during active conversion periods, reducing average power consumption.
Solution Approach 2:
The sample and hold circuit performs preliminary action by capturing and stabilizing the input signal before the actual conversion process begins. This preliminary sampling and holding allows the subsequent conversion stage to operate at a lower effective speed, reducing the clock frequency and power requirements for the critical conversion path while still supporting high overall sampling rates.
4Use of energy by moving object
If charge redistribution SAR ADC is used to reduce power consumption, then power consumption decreases, but the resolution is limited to 8 bits and large capacitors are required
Solution Approach 1:
The resolution requirement is segmented into two stages: the first stage provides coarse conversion (e.g., 4-6 bits) and the second stage provides fine conversion (remaining bits). This segmentation allows the use of charge redistribution techniques in the first stage for low power operation, while the second stage uses different circuitry optimized for high resolution, achieving overall 12-bit resolution without requiring all components to be high-power or large-capacitor based.
Solution Approach 2:
The patent combines charge redistribution SAR ADC technique with clocked switched-capacitor DAC architecture. The charge redistribution provides low-power operation for the coarse conversion, while the clocked switched-capacitor implementation enables higher resolution and faster operation in the fine conversion stage, merging the advantages of both approaches to achieve 12-bit resolution with reduced power consumption.
Data Source
AI summary
A method and apparatus for analog-to-digital conversion. An Analog-to-Digital Converter (ADC) includes M ADCj, j=1, 2, . . . , M. Each ADCj comprises a number of cells each of which comprises a first switch, a second switch, a current sink and an inverter. An inverter of a cell in an ADCj changes state in response to a current associate with an input signal of the ADCj exceeding a threshold, thus switching on the next cell. Each ADCj is enabled to perform analog-to-digital conversion on a residual current of a previous ADCj-1 after the previous ADCj-1 has completed its analog-to-digital conversion and has been disabled.