Clockless ADC Sampling for Low-Power Signal Conversion
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Solution Overview
Problem
Conventional analogue to digital converters (ADCs) have high power consumption and large size due to complex architectures required for time-sampling of analogue input signals, which is inefficient for portable devices and other applications where power conservation is critical, especially in monitoring battery voltage in devices like cellular phones and pacemakers.
Innovation Solution
The ADCs employ voltage or current sampling methods without the need for a clock, using an amplifier/subtracter, comparators, and a counter to detect variations in the analogue signal, allowing for reduced power consumption and simplified design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time-sampling ADC architecture is used, then the ADC can perform discrete time sampling of analogue input signals, but the power consumption and device size increase due to complex operations required at each sampling instant
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing lookup tables (LUTs) containing conversion data for different signal levels and transition scenarios. This pre-computed information is stored in memory structures within the ADC, allowing the converter to retrieve previously calculated conversion results rather than performing full complex operations at each sampling instant. The LUTs contain pre-computed transition data that enables the ADC to handle signal transitions efficiently without repeated complex calculations, thereby reducing power consumption while maintaining conversion accuracy.
2Productivity
If conventional time-sampling ADC architecture is used, then the ADC can convert analogue signals to digital signals at discrete time instants, but the device complexity and size increase due to sophisticated operations required at each sampling instant
Solution Approach 1:
The patent applies segmentation by dividing the conversion process into distinct functional blocks: a first counter for generating transition information, a second counter for tracking signal levels, memory structures for storing lookup tables, and control logic for coordinating operations. This modular segmentation allows each component to perform a specific simplified function rather than requiring a monolithic complex converter. The segmented architecture reduces overall device complexity while maintaining conversion speed through coordinated operation of these specialized sub-components.
Solution Approach 2:
The patent uses preliminary action by pre-computing and storing transition information in lookup tables before actual conversion operations. These pre-calculated transition data structures contain information about signal level changes and corresponding digital output transitions. During operation, the ADC retrieves this pre-computed information rather than performing complex real-time calculations, thereby reducing device complexity while maintaining high conversion speed through efficient data retrieval and counter operations.
3Use of energy by moving object
If voltage or current sampling without clock is used, then power consumption is reduced and design is simplified, but the ability to track rapid voltage changes may be limited
Solution Approach 1:
The patent applies feedback through continuous monitoring mechanisms that track signal level transitions in real-time. The counter-based architecture continuously compares the input signal against reference levels and automatically detects transitions, providing feedback-driven conversion without requiring external clock signals. This feedback mechanism ensures the ADC responds to rapid voltage changes as they occur, maintaining high response speed while operating in a low-power mode without clock signals.
Solution Approach 2:
The patent implements self-service through autonomous operation of the ADC that does not require external clock signals or complex control logic. The counter-based system automatically generates its own timing and control signals through the natural operation of the counters and comparators, enabling the ADC to self-regulate its conversion operations. This self-service capability allows the device to maintain accurate tracking of rapid voltage changes while consuming minimal power, as the conversion process is driven by the signal itself rather than external clocking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower power consumption, increased resolution through digital post-processing, reduced conversion times, and cost optimization, making the ADCs suitable for low-resource environments and applications requiring high speed and reduced resolution.
Implementation Method 1
an amplifier/subtracter, a signal sample and hold system, a first comparator, a second comparator
Implementation Method 2
a first comparator, a second comparator, and an N-bit counter
Data Source
AI summary
An analogue to digital converter (ADC) is provided which comprises an signal sampling device, a signal comparison device, and a digital signal generator. An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal.The signal sampling device may produce voltage samples or current samples of the analogue signal.