Clockless Delay Adaptation Loop Using Dual Autocorrelation Locking
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Solution Overview
Problem
Existing clockless delay adaptation loops for random data face challenges in maintaining consistent delay due to variations in voltage and temperature, and the use of reference voltage increases complexity and area.
Innovation Solution
A clockless delay adaptation loop is designed with two delay lines, an autocorrelator, and a controller, utilizing an XNOR gate and an OR gate to calculate autocorrelations that intersect at 0.5 unit intervals, eliminating the need for a reference voltage and reducing variations, with a controller generating control signals for the delay lines based on these autocorrelations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an autocorrelation control circuit with reference voltage is used for clockless delay adaptation, then delay adaptation can be achieved, but area and circuit complexity increase
Solution Approach 1:
The patent removes the reference voltage source from the autocorrelation control circuit, extracting only the essential autocorrelation computation functionality. This is achieved by using digital logic gates (XNOR and OR) to compute autocorrelation directly from the input signal and delayed signal, eliminating the need for external reference voltage while maintaining delay adaptation capability
Solution Approach 2:
The patent uses digital logic copies (XNOR gate and OR gate) to replicate the autocorrelation function that would traditionally require analog reference voltage. The XNOR gate computes one form of autocorrelation while the OR gate computes another form, and their outputs are combined to achieve the desired delay adaptation without complex analog circuitry
2Adaptability or versatility
If reference voltage is supplied to the autocorrelation control circuit, then delay adaptation works, but area increases
Solution Approach 1:
The reference voltage source and its associated distribution network are completely removed from the circuit. The autocorrelation control function is implemented purely through digital logic gates that operate directly on the signal levels, eliminating the area occupied by reference voltage generation and distribution infrastructure
Solution Approach 2:
The patent changes the operating parameters of the autocorrelation circuit from analog reference voltage levels to digital logic levels. By using XNOR and OR gates that operate with standard digital voltage levels, the circuit achieves the same functional outcome with significantly reduced area requirements
3Adaptability or versatility
If autocorrelation of input signal is used for delay adaptation, then delay can be adapted, but variation in adapted delay occurs due to voltage and temperature variations
Solution Approach 1:
The patent combines multiple autocorrelation computation paths (XNOR gate output and OR gate output) to create a composite control signal. This composite approach averages out the effects of voltage and temperature variations that would affect any single autocorrelation measurement, resulting in more stable delay adaptation across varying operating conditions
Solution Approach 2:
The patent implements a feedback mechanism where the autocorrelation outputs are continuously monitored and used to adjust the delay line settings. The controller receives the combined autocorrelation information and dynamically adjusts the delay to maintain optimal values despite environmental variations, creating a self-correcting system that improves reliability
Data Source
AI summary
A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.