Clock-Less Decision-Feedback Equalizer for RX Eye Scan

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Solution Overview

Problem

In high-speed data communication systems, traditional decision-feedback equalizers (DFE) face performance degradation due to the need for clock edge placement at the data center location, making it challenging to maintain optimal performance during receiver eye scan operations.

Innovation Solution

A clock-less DFE architecture utilizing a combining circuit and a feedback filter with a controllable delay circuit, which generates feedback signals by applying adjustable delay amounts to the equalized signal, allowing for post-cursor ISI cancellation without relying on clock-driven slicers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a typical DFE uses clock-driven slicers to achieve optimal performance, then the DFE performance is improved, but the system becomes dependent on precise clock edge placement at the data center location, making it difficult to perform RX eye scan

Engineering Contradiction:
ImproveDFE performanceVSAvoidRX eye scan capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent inverts the traditional clock-driven approach by using a clock-less DFE architecture. Instead of using clock edges to trigger slicers, the invention uses continuous-time feedback signals generated from the equalized output to cancel post-cursor ISI, eliminating the need for precise clock edge placement while maintaining equalization performance and enabling RX eye scan functionality

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts and removes the clock dependency from the DFE system. By eliminating the clock-driven slicer mechanism and replacing it with a continuous-time feedback filter that operates independently of clock edges, the system achieves both optimal DFE performance and RX eye scan capability without the traditional trade-off

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If the clock edge location is moved to perform RX eye scan, then the RX eye margin measurement is enabled, but the DFE performance is degraded due to deviation from the data center location

Engineering Contradiction:
ImproveRX eye margin measurementVSAvoidDFE performance
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a self-service mechanism where the feedback filter continuously generates correction signals based on the equalized output to cancel post-cursor ISI. This self-correcting mechanism operates independently of clock edge position, allowing the system to maintain optimal DFE performance while the clock can be freely positioned for RX eye scan measurements without degrading equalization performance

Inventive Principle:
Principle #25Self-service

3Object-generated harmful factors

If a typical DFE architecture is used, then the post-cursor ISI can be removed using past data bits, but the system requires precise clock synchronization which complicates the overall system design

Engineering Contradiction:
Improvepost-cursor ISI removalVSAvoidclock synchronization requirement
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical clock-synchronization system with a continuous-time signal processing approach. Instead of using discrete clock edges to sample and process data bits, the invention uses continuous feedback signals that operate throughout the entire bit period, eliminating the need for precise clock synchronization while maintaining the ability to remove post-cursor ISI

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP4254886A1Decision-feedback equalizer using feedback filter with controllable delay circuit and associated method
Publication Date: 2023.10.04 MEDIATEK INC
  • EP4254886A1 patent drawingFigure 1
  • EP4254886A1 patent drawingFigure 2
  • EP4254886A1 patent drawingFigure 3

AI summary

A decision-feedback equalizer (DFE) includes a combining circuit and a feedback filter. The combining circuit combines an input signal and at least one feedback signal to generate an equalized signal. The feedback filter generates the at least one feedback signal according to the equalized signal, and includes a controllable delay circuit. The controllable delay circuit receives an output signal that is derived from the equalized signal, and applies at least one delay amount to generate at least one delay signal, wherein the at least one feedback signal is derived from the at least one delay signal.