Clockless DFE Loop Reduces ISI in Multi-Level Signal Transmission
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Solution Overview
Problem
Signal integrity in data transmission systems is compromised by factors like bandwidth limitations and inter-symbol interference (ISI), particularly at high data rates, which limits transmission distances and requires complex equalization techniques.
Innovation Solution
A clockless decision feedback equalization (DFE) loop that combines multi-level input and feedback signals using a summation circuit, multi-bit quantizer, and analog delay circuits, applying signed DFE tap weights to reduce ISI and improve signal integrity without the need for clocked components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clocked DFE topologies are used to reduce ISI, then signal integrity is improved, but device complexity and circuit footprint increase
Solution Approach 1:
The patent extracts and eliminates the clock signal and associated clock recovery circuitry from the traditional DFE architecture. By removing these components, the circuit footprint is reduced while maintaining the core DFE functionality for ISI reduction through the feedback loop with delay elements and quantizers.
Solution Approach 2:
The clockless DFE system uses the inherent timing information present in the multi-level signal itself to drive the feedback loop operations. The signal's own transitions and levels provide the necessary timing reference, eliminating the need for external clock signals and clock recovery mechanisms.
2Length of stationary object
If bandwidth limitations are present in copper channels, then transmission distance is limited, but signal integrity deteriorates due to ISI
Solution Approach 1:
The patent implements a feedback mechanism where past signal levels are captured through delay elements, quantized to determine the transmitted symbol value, and then fed back through a summation node to subtract from the current received signal. This feedback loop compensates for ISI by removing the contribution of previously transmitted symbols from the current signal, thereby improving signal integrity and enabling longer transmission distances.
3Productivity
If data rate is increased to achieve higher signaling speed, then productivity improves, but ISI increases and signal integrity worsens
Solution Approach 1:
The system performs preliminary quantization of delayed signal levels to determine past symbol values before they cause interference to current symbol detection. By pre-determining the values of previously transmitted symbols through the quantizer paths, the system can proactively subtract their contribution from the current signal, preventing ISI from degrading signal integrity at high data rates.
Data Source
AI summary
An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.