Clockless Time-Interval Conversion with Binary Capacitor Array
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Solution Overview
Problem
Existing clock-based conversion methods for time intervals to digital words in high-energy efficiency systems, such as biomedical equipment and mobile devices, are energy-intensive and inefficient due to the need for clock signals and large capacitors, which occupy significant area and consume excessive energy.
Innovation Solution
A clockless apparatus using a control module with a set of capacitors and comparators, where the capacitance of each capacitor is halved, and a counter module with reduced counter capacitors, allowing for direct conversion of time intervals to digital words without a clock signal, reducing energy consumption and area usage by optimizing the linearization degree and current source efficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock-based conversion methods are used, then conversion accuracy can be maintained, but energy consumption increases significantly
Solution Approach 1:
The patent extracts and removes the clock signal generation and synchronization functions from the conversion system. By eliminating the clock signal source and using asynchronous event-driven operation, the system achieves accurate time interval measurement without the energy overhead of continuous clock signaling, directly resolving the contradiction between accuracy and energy consumption.
Solution Approach 2:
The conversion system performs self-synchronization through the natural timing events being measured. The start and stop events of the time interval automatically trigger the conversion process, eliminating the need for external clock control. This self-service mechanism maintains measurement accuracy while minimizing energy consumption by operating only when needed.
2Measurement precision
If large capacitors are used in the conversion apparatus, then measurement precision is improved, but area occupation increases
Solution Approach 1:
The patent segments the capacitor array into multiple smaller capacitors with binary-weighted values (C, 2C, 4C, 8C, etc.). This segmentation allows the system to achieve the same measurement precision as a single large capacitor while occupying significantly less area, as multiple small capacitors can be arranged more efficiently than one large capacitor.
Solution Approach 2:
The patent transitions from using a single large capacitor to using multiple capacitors arranged in a binary-weighted array. This dimensional change in the capacitor structure allows the system to maintain measurement precision while reducing area occupation through more efficient spatial arrangement and scaling.
3Measurement precision
If more capacitors are used to increase precision, then conversion accuracy improves, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple capacitors into a unified binary-weighted capacitor array controlled by a single control logic unit. This merging approach allows the system to achieve high conversion accuracy through the coordinated operation of multiple capacitors while minimizing device complexity by consolidating control functions and using systematic binary weighting patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves self-clocking capability without an energy-intensive clock signal, reducing the number and size of capacitors, lowering energy consumption by 28.75% to 41.02%, and minimizing parasitic capacitance effects, thereby enhancing the conversion process's accuracy and efficiency.
Implementation Method 1
a reference comparator and a signal comparator, wherein an output of the reference comparator is connected to a reference input of the control module and an output of the signal comparator is connected to a signal input of the control module
Implementation Method 2
a set of capacitors and a set of switches, wherein the capacitance of each capacitor of the set of capacitors is twice as low as the capacitance of its immediately preceding capacitor
Implementation Method 3
a reference current source and a signal current source, wherein an output of the reference current source is connected to a reference bus and an output of the signal current source is connected to a signal bus
Data Source
Figure 1
Figure 2~3
AI summary
An apparatus for clockless and direct conversion of a time interval to a digital word comprises: a control module (CM), two comparators (KR, KS), two current sources (IR, IS), two buses (R, S), two counter capacitors Cn-r, a set of n-r capacitors (Cn-r-1, ..., C0) with a binary capacitance ratio, two counter switches (Sn-r) and n-r switches of a set (Sn-r-1, ..., S0). The control module (CM) is equipped with an r-bit counter (Ct), whose outputs are connected directly to outputs of r most significant bits (bn-1, ..., br) of the n-bit output digital word (B).