Clockless Virtual GPIO Architecture for Pin Reduction
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Solution Overview
Problem
The existing GPIO architectures require a large number of pins for inter-processor communication (IPC), which increases manufacturing costs and limits GPIO availability for other system-level peripheral interfaces, as each symmetric sideband signal necessitates two GPIO pins for transmission and reception.
Innovation Solution
A virtual GPIO architecture that uses a pair of pins to transmit and receive virtual GPIO signals asynchronously, eliminating the need for a common clock and reducing the number of pins required, by employing a finite state machine with a ring oscillator for pulse-width modulation and demodulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of GPIO pins are used for inter-processor communication, then communication capability is improved, but manufacturing cost increases and GPIO availability for other interfaces decreases
Solution Approach 1:
Multiple virtual GPIO signals are merged and transmitted through a single physical communication channel using time-division multiplexing. The transmitter combines multiple GPIO signals into one serialized stream, and the receiver demultiplexes it back into individual virtual GPIO signals, allowing many logical pins to share one physical pin.
Solution Approach 2:
The patent transitions from spatial multiplexing (one pin per signal) to temporal multiplexing (multiple signals over time on one pin). By adding the time dimension to the communication channel, multiple signals that would normally require parallel physical pins can instead share a single pin across different time slots.
2Adaptability or versatility
If a large number of GPIO pins are used for inter-processor communication, then communication capability is improved, but GPIO availability for other system-level peripheral interfaces decreases
Solution Approach 1:
Multiple virtual GPIO signals are merged and transmitted through a single physical communication channel using time-division multiplexing. The transmitter combines multiple GPIO signals into one serialized stream, and the receiver demultiplexes it back into individual virtual GPIO signals, allowing many logical pins to share one physical pin.
Solution Approach 2:
A single physical pin serves multiple functions by acting as a communication channel for many virtual GPIO signals through time-division multiplexing. The same pin can transmit different GPIO signals at different time slots, making it a universal interface that replaces what would traditionally require multiple dedicated pins.
3Ease of operation
If synchronous transmission with common clock is used, then coordination between processors is simplified, but additional pins are required for clock signaling
Solution Approach 1:
Each processor generates its own local clock signal independently without requiring a common clock from the other processor. The system achieves synchronization through self-contained oscillators at each end, eliminating the need for dedicated clock pins while maintaining coordinated operation through the serialized data stream.
Solution Approach 2:
The common clock signal is extracted and removed from the physical pin requirements. Instead of transmitting clocks through dedicated pins, each processor uses its own locally generated clock, separating the clocking function from the data communication pins and reducing the total pin count required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient communication between integrated circuits using fewer pins, maintaining transparency of the transmitting node's health to the receiving node and enabling asynchronous transmission without the need for additional pins, thus reducing manufacturing costs and increasing GPIO availability.
Implementation Method 1
each FSM includes or associates with an oscillator such as a ring oscillator
Implementation Method 2
The transmitting FSM pulse-width modulates the transmitted signal over the dedicated transmit pin responsive to each bit in the transmit set by counting the oscillations from the oscillator
Data Source
AI summary
A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.