Closed-Loop Cascode Biasing for CMOS RF Amplifier Stability
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Solution Overview
Problem
Silicon-based CMOS cascode amplifier circuits face challenges in tolerating supply and bias voltage variations, bias current variations, and transistor stack height, particularly due to poor output resistance characteristics and low breakdown voltage, which affect RF performance and adaptability in changing RF environments.
Innovation Solution
The implementation of a cascode reference circuit with a closed loop bias control circuit that dynamically adjusts the gate bias voltage to maintain a consistent current multiple, accommodating arbitrary supply voltage variations and improving output resistance by matching drain and gate voltages across stages, while allowing for digital programmability to adapt to changing RF conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon-based CMOS transistors with short channel lengths are used, then fast RF response is achieved, but output resistance characteristics deteriorate due to drain voltage influence on gate
Solution Approach 1:
A cascode transistor is introduced as an intermediary element between the input transistor and the load. This cascode transistor shields the gate of the input transistor from drain voltage variations, thereby maintaining stable output resistance characteristics while preserving the fast RF response of short-channel CMOS transistors
Solution Approach 2:
The patent transitions from a single-transistor configuration to a two-transistor cascode configuration, adding a vertical dimension to the circuit architecture. This dimensional change isolates the gate voltage from drain voltage influence, improving output resistance while maintaining the speed benefits of short-channel devices
2Use of energy by moving object
If DC supply voltage is varied to optimize operation at different power levels, then power optimization is achieved, but amplifier performance deteriorates due to poor tolerance of supply voltage variations
Solution Approach 1:
A feedback mechanism is implemented that automatically adjusts the gate bias voltage in response to supply voltage variations. This feedback loop compensates for the effects of varying DC supply voltage, maintaining stable amplifier performance across different power levels and enabling effective power optimization
Solution Approach 2:
The bias circuit is designed to be dynamic rather than static, automatically adapting the gate voltage in response to changing supply conditions. This dynamic adjustment allows the amplifier to maintain optimal performance across a wide range of supply voltages, enabling power optimization without performance degradation
3Ease of manufacture
If breakdown voltage per device is low in silicon-based CMOS, then device integration is simplified, but voltage handling capability deteriorates
Solution Approach 1:
The voltage handling requirement is segmented across multiple transistors in the cascode configuration. Each transistor handles only a portion of the total voltage, allowing the use of low-breakdown-voltage silicon-based CMOS devices while achieving high overall voltage handling capability through the series connection of multiple devices
Data Source
AI summary
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.