Closed-loop clock calibration for low-power terminals

Solution Overview

Problem

Existing clock calibration methods in wireless communication systems are inefficient due to long calibration times, which increase standby power consumption and reduce sleep time in terminals, especially when using low-frequency clocks with lower accuracy and stability.

Innovation Solution

A closed-loop clock calibration method that adjusts the calibration factor based on the calibration error and sleep time period, allowing for more accurate clock calibration without relying on the system clock, thereby reducing calibration time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the system clock (high-frequency clock) is used as a calibration clock to calibrate the low-frequency clock, then the calibration accuracy is improved, but the calibration time becomes excessively long (more than 100ms)

Engineering Contradiction:

Improvecalibration accuracyVSAvoidcalibration time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts the calibration function from the system clock by introducing an independent calibration clock that operates separately from the system timing. This calibration clock is specifically dedicated to calibration operations, allowing calibration to proceed independently without being constrained by system clock requirements, thereby reducing calibration time while maintaining accuracy

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a calibration clock as an intermediary element between the low-frequency clock and the system clock. This calibration clock serves as a mediator that provides reference timing for calibration operations without directly interfering with system timing, enabling faster calibration by using a clock optimized specifically for calibration purposes rather than relying on the system clock

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If the calibration time is extended to ensure calibration accuracy, then the calibration accuracy is improved, but the sleep time of the terminal is reduced, increasing standby power consumption

Engineering Contradiction:

Improvecalibration accuracyVSAvoidstandby power consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the calibration function from the system clock by introducing an independent calibration clock that operates separately from the system timing. This calibration clock is specifically dedicated to calibration operations, allowing calibration to proceed independently without being constrained by system clock requirements, thereby reducing calibration time while maintaining accuracy

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs calibration operations using a dedicated calibration clock before the terminal enters sleep mode. By completing calibration in advance with a clock optimized for this purpose, the terminal can enter sleep mode sooner, extending the sleep duration and reducing overall power consumption while still achieving accurate calibration

Inventive Principle:

Principle #10Preliminary action

3Use of energy by stationary object

If the low-frequency clock is used to maintain system timing during sleep time period, then the power consumption is reduced, but the timing accuracy deteriorates due to temperature influence and lack of temperature compensation

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming accuracy

Core Design Contradiction:

Use of energy by stationary objectVSMeasurement precision

Solution Approach 1:

The patent introduces a calibration clock as an intermediary element between the low-frequency clock and the system clock. This calibration clock serves as a mediator that provides reference timing for calibration operations without directly interfering with system timing, enabling faster calibration by using a clock optimized specifically for calibration purposes rather than relying on the system clock

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where calibration results obtained using the calibration clock are used to adjust and compensate for timing drift in the low-frequency clock. This feedback loop allows the system to correct accuracy issues caused by temperature and environmental factors while maintaining the low power consumption benefits of using the low-frequency clock during sleep periods

Inventive Principle:

Principle #23Feedback

Data Source

PatentEP3249978B1Closed-loop clock calibration method, terminal and computer storage medium

Publication Date: 2019.02.27 SANECHIPS TECH CO LTD

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AI summary

Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an nth calibration period within the nth calibration period, and obtaining a calibration error of the nth calibration period; and according to the calibration error and calibration factor of the nth calibration period, obtaining a calibration factor of an (n+1)th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.