Closed-Loop Clock Generator for Duty Cycle and Jitter Control
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Solution Overview
Problem
Conventional clock generators for synchronous integrated circuits face issues with clock jitter, excessive power consumption, and slow operation due to the series arrangement of delay locked loops (DLLs) and duty cycle correction (DCC) circuits, which exacerbate timing errors and duty cycle errors at higher frequencies.
Innovation Solution
Implementing a clock generation circuit with DLL and DCC operations in parallel and utilizing closed-loop duty cycle correction to synchronize and correct the duty cycle of clock signals, reducing clock jitter and improving locking speed by adjusting delays in a closed-loop feedback mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but clock jitter and power consumption increase
Solution Approach 1:
The patent combines the DLL and DCC circuits into a single integrated clock generation circuit where both functions operate in parallel rather than series. The phase detector serves dual purposes by comparing both phase and duty cycle simultaneously, and the control circuit jointly adjusts delay elements to achieve both synchronization and duty cycle correction in one unified operation, thereby reducing overall power consumption while maintaining correction accuracy.
Solution Approach 2:
The phase detector is designed to perform multiple functions: it detects both phase differences and duty cycle errors using the same circuitry. The control circuit similarly handles both phase alignment and duty cycle correction tasks. This multi-functional approach eliminates the need for separate dedicated circuits for each function, reducing total power consumption while achieving both correction goals.
2Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but locking speed decreases
Solution Approach 1:
The patent merges phase detection and duty cycle detection into a single simultaneous operation performed by one phase detector. Both correction processes are initiated and completed together in parallel, eliminating the sequential execution inherent in series arrangements. This unified approach significantly accelerates the locking speed while maintaining accurate duty cycle correction.
Solution Approach 2:
The circuit performs preliminary detection of both phase and duty cycle conditions simultaneously at the start of the locking process. The control circuit prepares correction signals for both functions in advance and applies them concurrently, preventing the sequential delays that would otherwise occur during the locking process.
3Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but clock jitter increases
Solution Approach 1:
The patent integrates phase correction and duty cycle correction into a single coordinated operation. The unified control circuit ensures that both correction functions work together harmoniously rather than independently, preventing the accumulation of timing errors and jitter that occurs when separate circuits operate in series. This coordinated approach maintains clock signal stability while achieving accurate duty cycle correction.
4Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple separate circuits (DLL, DCC, phase detector, control circuit) into a single integrated clock generation circuit. By combining these functions into one unified structure with shared components, the overall device complexity is reduced while maintaining the capability to perform both phase synchronization and duty cycle correction effectively.
Data Source
AI summary
Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments.