Closed Loop Clock Synchronization for Network Reliability

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Solution Overview

Problem

Existing clock synchronization methods in network devices face challenges such as reliance on physical wiring for clock hierarchy, potential single points of failure, and increased complexity and CPU load when transferring reference clock information.

Innovation Solution

A closed loop configuration of network devices with clock connections allows for the distribution of a reference clock time in Coordinated Universal Time (UTC) format, enabling flexible designation of a local reference clock and reducing reliance on physical wiring or centralized entities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a centralized entity or physical wiring is used to establish clock hierarchy, then clock synchronization can be achieved, but the system becomes vulnerable to single points of failure and increases complexity

Engineering Contradiction:
Improveclock synchronization continuityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the centralized clock hierarchy into distributed peer-to-peer connections among network devices. Each device maintains independent clock connections with multiple peers, eliminating the single centralized authority and creating a resilient distributed timing network where failure of one device does not compromise overall synchronization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements redundant clock connections and pre-established peer relationships as a cushion against potential failures. Multiple independent clock paths are maintained in advance, so if one connection fails, alternative paths are already in place to maintain synchronization without interruption.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Measurement precision

If reference clock information is transferred through centralized entities or complex protocols, then synchronization is achieved, but CPU load and processing complexity increase

Engineering Contradiction:
Improvetiming accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the clock synchronization function from complex centralized protocols and implements it directly at the hardware level through dedicated clock connection interfaces. This removes the processing burden from the main CPU by handling timing operations through specialized circuitry and simplified peer-to-peer message exchange.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each network device autonomously maintains its own clock synchronization through direct peer-to-peer connections, without requiring centralized management or complex protocol processing. The devices self-organize and self-synchronize through simple mutual clock signal exchange, reducing overall system processing requirements.

Inventive Principle:
Principle #25Self-service

3Reliability

If physical wiring topology dictates clock hierarchy, then clock distribution is established, but adaptability and flexibility are reduced

Engineering Contradiction:
Improveclock distribution stabilityVSAvoidlocal reference clock designation flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic clock hierarchy where the role of reference clock can shift between devices based on operational needs. Any network device can be designated as the local reference clock through software configuration rather than being fixed by physical wiring, allowing the system to adapt to changing requirements while maintaining stable clock distribution through the established peer-to-peer connections.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12294469B2Boundary clock synchronized loop
Publication Date: 2025.05.06 MELLANOX TECHNOLOGIES LTD(IL)
  • US12294469B2 patent drawing
  • US12294469B2 patent drawing
  • US12294469B2 patent drawing

AI summary

In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.