Closed Loop Clock Synchronization for 5G Resilience
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Solution Overview
Problem
Current clock synchronization methods in network devices, such as SyncE, face limitations including a potential single point of failure and increased complexity due to reliance on physical wiring and centralized software entities, which can lead to inaccuracies and high CPU load, especially in 5G networks.
Innovation Solution
A closed loop configuration of compute nodes is established using clock connections to distribute a master clock frequency, allowing any compute node to be designated as the master clock, thereby maintaining synchronization even if one node fails, and utilizing clock synchronization circuitry with frequency synthesizers to discipline local clocks and ignore external clock signals when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a centralized master clock is used in traditional SyncE configuration, then clock synchronization can be achieved, but the system creates a single point of failure and increases device complexity
Solution Approach 1:
The patent segments the centralized master clock function into distributed master clock capabilities across multiple compute nodes. Each node can independently function as a master clock, eliminating the single point of failure while distributing the synchronization function across the network fabric.
Solution Approach 2:
The system dynamically selects which compute node serves as the master clock based on operational needs and failure conditions. The master clock role can transition between nodes, creating a dynamic rather than static synchronization architecture that improves resilience.
2Measurement precision
If physical wiring and centralized software entities are used for clock synchronization, then synchronization can be maintained, but CPU load increases and accuracy decreases
Solution Approach 1:
Each compute node independently performs clock synchronization operations using its own clock synchronization circuitry and frequency synthesizer. The nodes self-organize into a closed-loop synchronization network without requiring centralized software control, reducing CPU load and improving timing accuracy.
Solution Approach 2:
The patent replaces the mechanical/physical wiring-based SyncE approach with a software-defined closed-loop synchronization architecture that uses virtual clock connections. This substitution eliminates the need for precise physical wiring while reducing CPU overhead through efficient clock discipline algorithms.
3Reliability
If traditional SyncE with physical wiring is used, then clock frequency can be synchronized, but the system lacks resilience against node failures
Solution Approach 1:
The master clock function is made dynamic, allowing any compute node to assume the master clock role when needed. The system can adaptively redistribute the master clock function across different nodes based on operational requirements or failure conditions.
Solution Approach 2:
The system changes the operational parameters of the clock synchronization by allowing the master clock source to vary between different compute nodes. This parameter change enables flexible redistribution of the master clock function to maintain synchronization resilience.
4Measurement precision
If a closed loop configuration is implemented for master clock distribution, then synchronization accuracy improves, but the system complexity increases
Solution Approach 1:
The closed-loop clock connection architecture serves multiple functions: it provides timing accuracy through the closed loop, enables dynamic master clock selection, and offers failure resilience. This universal architecture achieves multiple goals without proportionally increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances clock synchronization resilience and accuracy by allowing seamless master clock redistribution and reducing CPU load, ensuring continuous operation and improved timing precision in 5G networks.
Implementation Method 1
The clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock
Data Source
AI summary
In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.