Closed Loop Current Controller for IC Core Frequency Adjustment
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Solution Overview
Problem
Current methods for controlling the maximum load current of integrated circuits (ICs) often result in frequency limitations that are not desirable, as they restrict all applications equally, even if only one application reaches the Icc limit, leading to performance issues and inefficient voltage regulator (VR) sizing.
Innovation Solution
A closed-loop control system using current sensors and a clock adjustment unit to dynamically adjust the effective frequency of the clock signal, allowing for precise control of current to the IC core, thereby limiting the VR output current to a target level without frequency restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If frequency limiting is used to control IccMax, then the VR size can be reduced, but all applications are restricted equally even if only one reaches the limit, hurting overall performance
Solution Approach 1:
The patent applies local quality by differentiating current control at the application level rather than globally. Each application's current consumption is measured independently via current sensors, and clock throttling is applied selectively only to applications exceeding their IccMax limits. This allows applications that do not reach their limits to maintain full performance while the VR size is optimized based on actual aggregated current usage patterns.
Solution Approach 2:
The system dynamically adjusts clock frequencies in real-time based on actual current consumption measurements. The closed-loop control continuously monitors current usage and adjusts clock throttling accordingly, allowing the system to adapt to changing workload conditions. This dynamic approach enables the VR to be sized for average current consumption rather than peak theoretical maximum, improving performance while reducing VR size.
2Area of stationary object
If IccMax is reduced to minimize VR size, then board die area is reduced, but frequency bins lose frequency headroom without reaching the limit
Solution Approach 1:
The patent changes the control parameter from static frequency limiting to dynamic current-based clock throttling. Instead of pre-defining frequency bins with conservative IccMax limits, the system measures actual current consumption and adjusts clock frequency dynamically. This allows frequency bins to be set higher since the closed-loop control will throttle clock speed only when actual current consumption approaches the limit, effectively decoupling the VR size from conservative frequency headroom.
3Ease of manufacture
If conservative IccMax limits are set for all applications, then VR sizing is simplified, but applications that do not reach the limit suffer performance degradation
Solution Approach 1:
The patent implements feedback through current sensors that continuously measure actual current consumption of each application and feed this information back to the clock control mechanism. This closed-loop feedback enables the system to set more aggressive IccMax limits in VR sizing since the actual current usage will be monitored and clock throttling applied only when necessary. The feedback mechanism replaces the need for conservative static limits with dynamic, measurement-based control.
Data Source
AI summary
A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.