Closed-Loop DVFS Voltage Control for IC Timing Margin
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Solution Overview
Problem
Current dynamic voltage and frequency scaling (DVFS) methods in integrated circuit (IC) devices lead to increased power consumption and temperature rises due to the need for extra voltage margins to compensate for di/dt noise, which degrades reliability and performance.
Innovation Solution
A closed-loop dynamic voltage and frequency scaling (CL_DVFS) system that automatically adjusts the core supply voltage and frequency to optimize power management by using a digitally parameterizable voltage controlled oscillator (DVCO) and a cycle-error integrator to detect and correct frequency errors, allowing each component to operate at its optimal voltage for a given frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra voltage margin is added to compensate for di/dt noise, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage adjustment by continuously monitoring timing margins and adjusting the supply voltage in real-time. Instead of using a fixed extra voltage margin, the system dynamically scales voltage based on actual operating conditions, thereby maintaining reliability while reducing unnecessary power consumption during periods when large voltage margins are not required.
Solution Approach 2:
The system employs feedback mechanisms by monitoring timing margin measurements and using this information to adjust the supply voltage. The timing margin monitor continuously measures whether timing constraints are met, and this feedback drives the voltage adjustment process, ensuring that voltage is increased only when necessary to maintain reliability, thus avoiding excessive power consumption.
2Reliability
If extra voltage margin is added to compensate for di/dt noise, then timing margins are maintained, but temperature rises
Solution Approach 1:
The system dynamically adjusts voltage based on actual timing margin requirements rather than maintaining a static elevated voltage level. This dynamic approach ensures timing margins are maintained when needed while reducing voltage (and thus heat generation) during periods when lower voltages are sufficient, thereby controlling temperature rises.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on measured timing margins. By adjusting the voltage parameter in response to actual operating conditions rather than maintaining a fixed high voltage, the system maintains timing margins while minimizing temperature increases that would result from continuously operating at elevated voltage levels.
3Device complexity
If DVFS tables are defined in software with quantized voltage levels, then device complexity is reduced, but manufacturing precision is compromised
Solution Approach 1:
The system performs self-characterization by automatically measuring its own timing margins and determining optimal voltage levels during operation. This self-service approach eliminates the need for external precision voltage characterization and binning processes, achieving both low device complexity and high effective precision through runtime adaptation rather than manufacturing-time precision.
Data Source
AI summary
A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.