Closepath Fast Incremented Sum in Three-Path Fused Multiply-Add Design
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Solution Overview
Problem
The IEEE 754 standard for floating-point arithmetic faces challenges in representing and computing denormal numbers, which can result in significant mathematical errors due to limitations in the exponent portion, particularly for numbers with exponents smaller than -126, leading to difficulties in processing subnormal numbers.
Innovation Solution
A floating-point multiply-accumulate unit with a close path adder that includes an unincremented mantissa addition circuit and an incremented mantissa addition circuit, operating in parallel to produce a close path result by selecting between unincremented and incremented mantissa results, addresses the representation and computation of denormal numbers by partitioning the data-path into three paths and eliminating the need for massive alignment and complementation stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 754 standard floating-point representation is used, then standard compliance and wide range of values are supported, but denormal numbers cause significant mathematical errors due to exponent limitations
Solution Approach 1:
The patent segments the floating-point addition process into three distinct paths: (1) normal path for standard IEEE 754 operations, (2) close path for denormal number handling with unincremented mantissa, and (3) close path with incremented mantissa. This segmentation allows each path to be optimized for its specific operand type, resolving the contradiction by providing reliable accurate computation for normal numbers while maintaining adaptability for denormal numbers through the specialized close paths.
Solution Approach 2:
The patent applies preliminary action by pre-computing both unincremented and incremented mantissa results in parallel before the final selection stage. The close path adder anticipates the need for mantissa adjustment by preparing both possibilities simultaneously, allowing the selection circuit to choose the correct result based on overflow conditions without requiring post-computation correction, thus ensuring both accuracy and adaptability.
2Productivity
If traditional floating-point addition with alignment and complementation stages is used, then IEEE 754 compliance is maintained, but processing speed is reduced due to sequential computation
Solution Approach 1:
The patent implements preliminary action by pre-computing both unincremented and incremented mantissa results in parallel using separate addition circuits. This allows the selection circuit to quickly choose the correct result based on overflow conditions without requiring sequential correction steps, thereby improving processing speed while maintaining computation accuracy through the parallel preparation of both possible outcomes.
Solution Approach 2:
The patent applies dynamics by implementing a dynamic selection mechanism that adapts the computation path based on the actual operand values and overflow conditions. The selection circuit dynamically chooses between unincremented and incremented mantissa results, and between different path combinations (normal vs. close path), allowing the system to optimize for speed when denormal numbers are detected while maintaining accuracy through conditional path selection.
3Productivity
If parallel computation of unincremented and incremented mantissa results is implemented, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the adder circuit into specialized modules: a normal path adder for standard operations, and a close path adder with separate unincremented and incremented mantissa addition circuits. This segmentation organizes the complexity into manageable, functionally distinct blocks that can be independently optimized and controlled, reducing the overall device complexity while maintaining parallel computation capabilities for improved speed.
Data Source
AI summary
According to one general aspect, an apparatus may include a floating-point multiply-accumulate unit configured to generate a floating point result by either adding or subtracting three floating point operands: an addend, a product carry, and a product sum. The floating-point multiply-accumulate unit may include a close path adder. The close path adder may include an unincremented mantissa addition circuit configured to compute an unincremented mantissa result based upon the three floating point operands. The close path adder may also include an incremented mantissa addition circuit configured to, at least partially in parallel with the mantissa addition circuit, produce an incremented mantissa result. The close path adder may further include a selection circuit configured to produce a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.