Cloud FPGA Bitstream Caching Using Embedding-Based Prefetching

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Solution Overview

Problem

Current data centers do not allow sharing of FPGAs among multiple tenants at runtime, limiting the efficient use and revenue generation from reconfigurable hardware resources, and traditional cache systems based on temporal and spatial locality principles are inefficient in cloud marketplaces.

Innovation Solution

A network-based apparatus that selects and stores FPGA bitstreams based on an embedding matrix mapping bitstreams to N-dimensional vectors, allowing for efficient caching and execution of bitstreams likely to be used together by assigning similar pointers and using a decision tree for cache management, enabling efficient storage and rapid access in cloud marketplaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional cache systems based on temporal and spatial locality principles are used, then cache management is simple, but cache efficiency is low in cloud marketplaces

Engineering Contradiction:
Improvecache efficiencyVSAvoidcache management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transforms the cache management approach by changing from traditional temporal/spatial locality parameters to embedding-based similarity parameters. Bitstreams are mapped to N-dimensional vectors where distance indicates execution similarity, enabling more efficient prefetching decisions that adapt to cloud marketplace workloads

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an embedding matrix as an intermediary layer between bitstreams and cache management. This matrix maps bitstreams to vector representations, serving as a mediator that enables sophisticated similarity-based prefetching without requiring complex direct analysis of bitstream execution patterns

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If FPGAs are shared among multiple tenants at runtime, then resource utilization and revenue generation improve, but system complexity and management difficulty increase

Engineering Contradiction:
Improveresource utilizationVSAvoidsystem management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the FPGA resource management into distinct components: bitstream storage, embedding matrix maintenance, probability calculation, and cache management. This segmentation allows multi-tenant sharing while distributing management complexity across modular components rather than requiring monolithic control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-computing embedding vectors for bitstreams and maintaining an embedding matrix in advance. When bitstreams are requested, the system can quickly calculate execution probabilities and prefetch relevant bitstreams without complex real-time analysis, simplifying runtime management

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If bitstreams are selected based on embedding matrix and execution probability, then prefetching accuracy improves, but computational overhead increases

Engineering Contradiction:
Improveprefetching accuracyVSAvoidcomputational overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent applies partial action by selecting only the top-K most probable bitstreams for prefetching based on embedding similarity, rather than analyzing all possible bitstream combinations. This provides high prefetching accuracy with reduced computational overhead by focusing on the most relevant candidates

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3993270A1Management and implementation of applications in cloud-based fpgas
Publication Date: 2022.05.04 NOKIA SOLUTIONS & NETWORKS OY
  • EP3993270A1 patent drawingFigure 1
  • EP3993270A1 patent drawingFigure 2
  • EP3993270A1 patent drawingFigure 3

AI summary

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network-based apparatus to: select at least a first bitstream from a central repository based on an indicator associated with a probability of concurrent, simultaneous or future execution of the first bitstream and a second bitstream at a network node, each of the first bitstream and the second bitstream including programming information for a device at the network node, the indicator being based on an embedding matrix mapping at least a subset of bitstreams in the central repository to an N-dimensional vector of real numbers; and output the first bitstream to the network node for storage and execution upon request.