Cloud FPGA Bitstream Verification With Dual Roots of Trust
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Solution Overview
Problem
Cloud-based FPGA deployment faces security concerns due to hardware asset vulnerabilities, including remote physical side-channel attacks and information leakage, with malicious actors potentially stealing sensitive information and launching intellectual property counterfeit.
Innovation Solution
Implementing a dual-root-of-trust system comprising a tenant-side root of trust (TSRoT) and a cloud FPGA provider-side root of trust (CFPRoT) to ensure secure deployment, using encryption and hash verification to authenticate and protect hardware designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cloud-based FPGA deployment is implemented to enable hardware acceleration services, then processing speed and power efficiency are improved, but security vulnerabilities increase due to shared power distribution network and fabric access
Solution Approach 1:
The patent segments the trust verification process into two independent roots of trust: tenant-side root of trust (TSRoT) and cloud FPGA provider-side root of trust (CFPRoT). This segmentation allows each party to independently verify the other's integrity without compromising the shared hardware infrastructure, thereby maintaining security in the cloud-based FPGA deployment model.
Solution Approach 2:
The patent introduces hash verification mechanisms and encrypted bitstream transmission as intermediary layers between the tenant and cloud provider. These intermediaries enable secure communication and verification without requiring direct trust in the shared power distribution network or fabric, thus resolving the security vulnerabilities while preserving processing speed benefits.
2Adaptability or versatility
If design contents are made accessible to cloud providers for deployment, then deployment flexibility is improved, but risk of intellectual property theft and bitstream tampering increases
Solution Approach 1:
The patent implements preliminary hash verification of design contents and bitstreams before deployment. The tenant-side root of trust (TSRoT) computes and verifies hashes of design contents prior to making them accessible to the cloud provider, ensuring that any subsequent tampering can be detected. This preliminary action enables deployment flexibility while preventing intellectual property theft.
Solution Approach 2:
The patent establishes a feedback mechanism where the cloud FPGA provider-side root of trust (CFPRoT) continuously verifies bitstream integrity through hash comparison after deployment. This feedback loop ensures that any unauthorized modifications to the design contents are detected and prevented, maintaining both deployment flexibility and IP protection.
3Reliability
If security verification mechanisms are implemented to protect hardware designs, then security and integrity are improved, but runtime overhead increases
Solution Approach 1:
The patent moves the computationally intensive hash verification and encryption operations to the deployment phase rather than runtime. The tenant-side root of trust (TSRoT) performs bitstream encryption and hash computation before deployment, and the cloud provider-side root of trust (CFPRoT) performs initial verification upon receipt. This preliminary action significantly reduces runtime overhead while maintaining security and integrity.
Solution Approach 2:
The patent uses hash values as compact copies of the original design contents for verification purposes. Instead of continuously verifying the entire bitstream at runtime, the system verifies the hash copy, which is computationally much less intensive. This copying approach maintains reliability while minimizing runtime overhead.
Data Source
AI summary
A method and system are directed to enabling tenant-side design checks for cloud field-programmable gate array (FPGA) deployment. A pseudo-trusted execution environment is created at a tenant device to tie a hash of a compiled bitstream to a hash of design rule or virus scan results, which is sent along with an encrypted version of a bitstream to a cloud provider device that recovers the hash of the design and forwards the encrypted bitstream to a root-of-trust (RoT) on a FPGA to program. The RoT checks the hash provided by the cloud provider device against a supplied bitstream from the tenant device to confirm they match before programming.