Cloud FPGA Graph Acceleration for GNN Memory Access

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Solution Overview

Problem

Existing systems face inefficiencies in accessing and processing graph data due to random memory accesses, which can lead to high costs and reduced performance in graph neural network (GNN) processing.

Innovation Solution

A system comprising a host with a circuitry board that includes an access engine circuitry, which fetches structure and attribute data from pinned memory via PCIe connections, performs node sampling, and sends the data to processors for GNN processing, thereby optimizing memory allocation and access for sparse matrix multiplications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If graph data is stored in memory for GNN processing, then data availability is improved, but random memory access patterns cause high costs and reduced performance

Engineering Contradiction:
Improvedata availabilityVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The access engine performs preliminary actions by fetching and preprocessing graph data (structure data and attribute data) before the actual GNN processing occurs. It proactively retrieves data from memory, performs node sampling to identify relevant nodes, and prepares the data in an optimized format, thereby eliminating the need for random access patterns during the actual processing phase and improving overall system performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The access engine acts as an intermediary component between the memory system and the GNN processing units. It mediates the data flow by receiving requests from the processing system, fetching data from memory, performing node sampling to filter relevant data, and delivering the processed data to the GNN processing units. This intermediary role transforms random access patterns into structured, efficient data retrieval operations

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If all graph data is fetched for processing, then completeness is improved, but data transmission volume and processing time increase

Engineering Contradiction:
Improvedata completenessVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The access engine extracts only the necessary portion of graph data by performing node sampling. Instead of fetching and processing all graph data, it identifies and extracts the subset of data corresponding to sampled nodes that are relevant for the specific GNN processing task. This extraction principle reduces data transmission volume and processing time while maintaining the completeness of the required data subset

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system applies partial action by fetching and processing only a portion of the graph data corresponding to sampled nodes rather than the entire graph. The node sampling mechanism determines the appropriate subset of nodes and their associated attribute data, enabling the system to perform GNN processing with partial data that is sufficient for the task at hand, thereby reducing processing time and resource consumption

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12332828B2Graph acceleration solution with cloud FPGA
Publication Date: 2025.06.17 ALIBABA (CHINA) CO LTD
  • US12332828B2 patent drawing
  • US12332828B2 patent drawing
  • US12332828B2 patent drawing

AI summary

This application describes systems and methods for facilitating memory access for graph neural network (GNN) processing. An example method includes fetching, by an access engine circuitry implemented on a circuitry board, a portion of structure data of a graph from a pinned memory in a host memory of a host via a first peripheral component interconnect express (PCIe) connection; performing node sampling using the fetched portion of the structure data of the graph to select one or more sampled nodes; fetching, by the access engine circuitry, a portion of attribute data of the graph from the pinned memory via the first PCIe connection; sending the fetched portion of the attribute data of the graph to one or more processors; and performing, by the one or more processors, GNN processing for the graph using the fetched portion of the attribute data of the graph.