Cluster-on-chip Message Passing via Software Cache Coherency
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Solution Overview
Problem
Cluster-on-chip computing environments face challenges in programmability due to the lack of hardware cache coherency between processor cores, which affects message passing and scalability, especially when a large number of cores are integrated on a single chip.
Innovation Solution
The implementation of a cluster-on-chip computing environment with a mesh network architecture that partitions the operating system into independent kernels, allowing each processor core to execute a kernel, and supports message passing through models that include hierarchical memory, caching, and software-managed cache coherency, enabling efficient communication between nodes without relying on hardware cache coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hardware cache coherency is implemented in cluster-on-chip systems, then message passing between nodes becomes simpler, but device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent introduces a software intermediary (kernel-level message passing interface and cache coherency management layer) that mediates between nodes without requiring hardware cache coherency. This software layer handles cache invalidation, message routing, and synchronization, allowing nodes to communicate efficiently without complex hardware support for cache coherency across the mesh network.
2Productivity
If the number of processor cores is increased on a single chip, then computing power and productivity increase, but conventional multi-core techniques for message passing and cache coherency fail to scale
Solution Approach 1:
The patent segments the operating system into multiple independent kernels, each running on a subset of processor cores. Each kernel manages its own cache and memory space, and inter-kernel communication occurs through standardized message passing interfaces. This segmentation allows the system to scale to many cores without requiring global cache coherency, as each kernel operates semi-independently with well-defined communication protocols.
Solution Approach 2:
The patent transitions from a traditional two-dimensional cache coherency problem (managing cache states between a limited number of cores) to a multi-dimensional message passing architecture where communication occurs through standardized interfaces across the mesh network. This dimensional shift allows scaling to hundreds of cores by treating each node as an independent communication entity rather than requiring direct cache coherency management between all core pairs.
3Reliability
If hardware cache coherency is implemented across all nodes, then data consistency is improved, but loss of time due to coherency protocols and mesh network communication increases
Solution Approach 1:
The patent implements self-service cache coherency where each node's kernel independently manages its own cache state and initiates coherency operations only when necessary. Instead of a centralized coherency protocol that all nodes must participate in continuously, each kernel tracks its own cache invalidations and sends targeted invalidation messages to other kernels only when data consistency is actually required, reducing overall communication overhead and latency.
Data Source
AI summary
Technologies pertaining to cluster-on-chip computing environments are described herein. More particularly, mechanisms for supporting message passing in such environments are described herein, where cluster-on-chip computing environments do not support hardware cache coherency.