Cluster-Based Bit Flipping for PRML Error Correction
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Solution Overview
Problem
Conventional bit flipping technologies for hard disk drives, such as low-density parity check (LDPC) decoders, increase system complexity and data inefficiency due to the need for separate encoders and decoders, which complicates error correction in high-density storage systems like bit pattern media recording (BPMR).
Innovation Solution
A bit flipping device and method that generates input data sequences based on a two-dimensional array pattern, classifies them into clusters using the K-mean algorithm, and performs bit flipping on erroneous bits within these clusters, reducing system complexity and data inefficiency by integrating clustering and bit flipping units with a PRML detector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit flipping technology (LDPC decoder) is used, then error correction capability is improved, but system complexity increases due to requiring separate encoder and decoder
Solution Approach 1:
The patent combines the encoder and decoder into a single integrated device that performs both functions. The encoding unit generates codewords with embedded error correction capabilities, while the decoding unit uses the same device to detect and correct errors, eliminating the need for separate encoder and decoder hardware.
Solution Approach 2:
The single device performs multiple functions: it acts as both an encoder for generating codewords and a decoder for error correction. The same processing unit and memory structures are utilized for both encoding and decoding operations, making the device universal and multi-functional.
2Reliability
If conventional bit flipping technology (LDPC decoder) is used, then error correction capability is improved, but data inefficiency increases
Solution Approach 1:
The encoding unit performs preliminary action by embedding error correction information directly into the codeword structure during the encoding phase. Parity bits and check symbols are pre-calculated and positioned within the codeword, so that no additional data transmission or processing is needed for error correction, thereby improving data efficiency.
3Quantity of substance
If inter-island spacing is reduced to increase areal density, then storage capacity is improved, but inter-symbol interference and inter-track interference increase
Solution Approach 1:
The decoding unit uses feedback mechanisms to detect interference patterns in the readback signal. By analyzing error patterns and using the pre-encoded check symbols, the system can identify and correct errors caused by inter-symbol and inter-track interference, allowing the use of reduced spacing while maintaining data integrity.
Data Source
AI summary
Provided are a bit flipping device and method and a computer readable program for the same. The bit flipping device for input data having a two-dimensional array pattern includes: a clustering unit configured to generate at least one input data sequence based on the two-dimensional array pattern of the input data and classify the input data sequence into at least one cluster according to a preset method; and a bit flipping unit configured to perform bit flipping on erroneous bits in the input data sequence based on the classified cluster. Therefore, it is possible to further reduce inefficiency while further reducing system complexity compared to the existing error correction code-based bit flipping method by coupling the bit flipping device to an output side of a partial response maximum likelihood (PRML) detector to classify an output value of the PRML detector into at least one cluster and perform bit flipping based on the classified result.