Clustered Chiplet Hub Architecture for Scalable Memory Access
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Solution Overview
Problem
Chiplet-based systems are limited to a few large manufacturers due to proprietary interconnections, preventing small to medium entities from realizing the performance and cost benefits of chiplet technology, and SoCs face yield and optimization challenges with complex designs.
Innovation Solution
A chiplet hub architecture that integrates multiple specialized chiplets with a central fabric, utilizing a hub manager and HDMA controller to facilitate interconnectivity and memory management, allowing for flexible, scalable, and efficient chiplet-based systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If proprietary chiplet interconnections are used, then manufacturing precision and device complexity are controlled for large manufacturers, but adaptability and ease of manufacture are reduced for small to medium entities
Solution Approach 1:
The patent applies universality by creating a standardized chiplet interconnection system that serves multiple purposes: it enables both large manufacturers and small to medium entities to build chiplet-based systems, supports various chiplet configurations, and provides a common platform for diverse applications. This standardized interface acts as a universal connector that maintains manufacturing precision while dramatically improving adaptability and accessibility across different organization sizes.
2Device complexity
If monolithic SoC designs are used, then device complexity is reduced to a single integrated circuit, but manufacturing precision and yield deteriorate due to large die size
Solution Approach 1:
The patent applies segmentation by dividing the monolithic SoC into multiple smaller, independent chiplets that can be manufactured separately on smaller dies with higher yield. These segmented chiplets are then interconnected through standardized interfaces to form the complete system functionality. This segmentation maintains the functional integration of an SoC while improving manufacturing precision and yield by avoiding the need for a single large-die fabrication process.
3Device complexity
If monolithic GPU designs are used, then device complexity is simplified to a single chip, but manufacturing precision and cost deteriorate due to extremely large die size
Solution Approach 1:
The patent applies segmentation to GPU design by breaking down the monolithic GPU into multiple smaller GPU chiplets that can be manufactured on smaller dies with higher yield. These segmented GPU chiplets are interconnected through standardized interfaces to deliver the computational power of a full GPU while improving manufacturing precision and reducing costs associated with large-die fabrication.
4Reliability
If specialized semiconductor processes are used for different functions, then performance is improved for each function, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by creating a standardized interconnection platform that can accommodate multiple specialized chiplets with different semiconductor processes. This universal interface allows various high-performance chiplets (GPU, CPU, memory, I/O) manufactured with process-optimized techniques to be integrated into a single system without requiring complex custom interconnection designs for each combination, thereby maintaining performance while reducing overall system complexity.
Data Source
AI summary
A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.