Clustered Memory Cells Reduce Bit Line Count
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in integrating memory cells into CMOS manufacturing processes due to the need for additional processing steps and masks, leading to increased costs and limitations in area requirements and program/erase cycles.
Innovation Solution
A non-volatile memory device with clustered memory cells using single-polysilicon-layer floating gate MOS transistors, where direct and complementary memory cells are aligned in separate rows and sub-clusters, reducing the number of bit lines required for column addressing and optimizing cell pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate cells use additional polysilicon level relative to standard CMOS process flows, then non-volatile memory functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses a single polysilicon layer for both the floating gates of memory cells and the gate regions of MOS transistors, eliminating the need for additional polysilicon levels and simplifying the manufacturing process while maintaining non-volatile memory functionality
2Reliability
If additional processing steps and masks are used for non-volatile memory integration, then memory functionality is achieved, but manufacturing cost increases
Solution Approach 1:
By using a single polysilicon layer for both memory cell floating gates and transistor gate regions, the patent eliminates additional processing steps and masks, reducing manufacturing cost while maintaining memory functionality
3Speed
If cost-effective non-volatile memory cells use select MOS transistors for capacitively coupling, then programming speed is improved, but power consumption and area occupation increase
Solution Approach 1:
The patent removes the select MOS transistor from the memory cell structure, using only the essential floating gate and control gate components, thereby reducing cell area while maintaining programming speed through direct charge injection mechanisms
4Reliability
If complementary cells are used to store one bit with differential reading, then reliability and error reduction are improved, but the number of required bias electrical-coupling lines and array design complexity increase
Solution Approach 1:
The patent merges the storage function of complementary cells with a simplified addressing scheme where clusters of cells share common bit lines and control gates, reducing the number of bias electrical-coupling lines required while maintaining differential reading capability for error reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces area requirements and bit line constraints, enabling more efficient integration and programming of memory cells while maintaining reliability and extending the number of program/erase cycles.
Implementation Method 1
each bit is represented by a respective floating gate charge state of a respective memory cell
Implementation Method 2
a bipolar transistor may be used for program operations by injection of hot electrons
Implementation Method 3
erasure is typically based on the Fowler-Nordheim effect
Data Source
AI summary
An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.