CMAC System for Convolution with Dynamic Resource Scaling
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Solution Overview
Problem
Conventional systems face challenges in performing real-time convolution operations for both 2D and 3D images due to limited on-chip resources and require fully configurable, low-level complex processing elements that can adapt to varying computation demands.
Innovation Solution
The implementation of a Convolution Multiply and Accumulate (CMAC) system utilizing on-chip resources such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC), which performs convolution operations by multiplying feature matrices with depth information, accumulating results, and filtering through predefined functions, allowing for adaptable kernel sizes and efficient resource reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional systems are used to perform convolution operations, then the system can process images, but the computation becomes difficult due to limits of available on-chip resources
Solution Approach 1:
The system is divided into multiple processing elements (PEs) that can be configured in different arrangements. Each PE handles a portion of the convolution computation, allowing the system to scale computation performance by activating appropriate numbers and types of PEs based on available on-chip resources
Solution Approach 2:
The system provides dynamic configurability where processing elements can be enabled or disabled based on real-time resource availability and computation demands. The same hardware can adapt its operational state to match varying workload requirements, optimizing the balance between computation performance and resource constraints
2Adaptability or versatility
If different systems are implemented for 2D and 3D image computation, then each system can be optimized for its specific task, but the overall system complexity increases
Solution Approach 1:
The processing elements are designed with universal functionality to handle both 2D and 3D convolution operations. By configuring the same PE architecture with different kernel parameters and data flow arrangements, the system can adapt to process various image dimensions without requiring separate dedicated systems for each task
3Productivity
If hardware capabilities are extended in real time, then computation demand can be met, but the on-chip resources are limited and cannot be extended
Solution Approach 1:
The system changes operational parameters such as kernel size, stride, and processing element activation states to adapt computation capacity to available resources. By adjusting these parameters dynamically, the system can optimize computation performance within the fixed physical constraints of on-chip resources without requiring hardware extension
Data Source
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AI summary
A Convolution Multiply and Accumulate (CMAC) system for performing a convolution operation is disclosed. The CMAC system receives image data pertaining to an image. The image data comprises a set of feature matrix, a kernel size and depth information. Further, the CMAC system generates a convoluted data based on convolution operation for each feature matrix. The CMAC system performs an accumulation of the convoluted data to generate accumulated data, when the convolution operation for each feature matrix is performed. The CMAC system further performs an addition of a predefined value to the accumulated data to generate added data. Further, the CMAC system filters the added data to provide a convolution result for the image, thereby performing the convolution operation of the image.