CMB Hybrid SRAM/DRAM Caching for Read/Write Commands
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CMB performance is limited by traditional cache mechanisms that are not adapted to CMB, leading to low hit-rates and increased latency, and using wider DRAM interfaces or additional SRAM increases costs without improving efficiency.
Innovation Solution
A hybrid SRAM/DRAM data path is used for CMB caching, where read commands are processed in SRAM and write commands in DRAM, with data being deleted after host access to free up space for subsequent commands, and maintaining PRP/SGL pointers for high hit-rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache mechanisms (e.g., LRU) are used for CMB, then the system can maintain existing memory structures, but the hit-rate is low and latency is high
Solution Approach 1:
The patent changes the fundamental parameter of cache management from traditional LRU algorithms to a CMB-specific mechanism that leverages the NVMe submission/completion queue structure. The cache management is tied to command completion status rather than access patterns, fundamentally changing how cache hits and misses are determined.
Solution Approach 2:
The patent makes the CMB serve multiple functions simultaneously: it acts as both a cache for frequently accessed data and a buffer for NVMe command processing. The same memory structure handles both caching operations and command queue operations, eliminating the need for separate cache management hardware.
2Quantity of substance
If a larger SRAM is dedicated for CMB to improve performance, then the CMB size increases, but the controller cost increases significantly
Solution Approach 1:
The patent merges the CMB functionality with the existing DRAM used for metadata storage. Instead of using separate SRAM for CMB, the system combines both functions into a single DRAM structure, reducing overall memory requirements and controller cost while maintaining CMB performance.
Solution Approach 2:
The patent creates a composite memory structure that combines SRAM and DRAM characteristics in a unified CMB implementation. The system uses DRAM for bulk storage with SRAM-like speed characteristics achieved through clever cache management, effectively creating a composite memory solution that balances cost and performance.
3Productivity
If a wider DRAM interface (e.g., 64-bit bus width) is used to increase bandwidth, then the raw DRAM bandwidth efficiency improves, but the controller cost and DRAM costs increase
Solution Approach 1:
The patent applies partial action by using a narrower DRAM interface (32-bit) than what would be required for full CMB performance, but compensates through intelligent cache management that maximizes the utilization of available bandwidth. The system achieves sufficient performance without the excessive cost of a wider interface.
Data Source
AI summary
A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.