Compressed Memory Controller LLC Sub-line Segmentation
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Solution Overview
Problem
Memory bandwidth limitations in CPU-based systems lead to increased latency due to queuing of memory access requests, as conventional memory bandwidth compression schemes are restricted by the memory read/write granularity, limiting the number of available 'bins' for data compression.
Innovation Solution
Implementing a compressed memory controller (CMC) that utilizes multiple last-level cache (LLC) lines to compress and store data in system memory, allowing for a larger number of bins by pre-fetching and compressing data across sub-lines within an LLC line, thereby optimizing memory bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory bandwidth compression schemes are used with memory read/write granularity constraints, then memory bandwidth is reduced, but the number of available bins for compression is limited
Solution Approach 1:
The patent divides an LLC line into multiple sub-lines, where each sub-line can be independently marked as valid. This segmentation allows the system to create more bins for compression than the memory read/write granularity would normally permit, directly resolving the contradiction between increasing the number of bins and maintaining simple memory architecture.
2Speed
If memory access requests are queued due to memory bandwidth limits, then memory bandwidth is protected, but access latency increases
Solution Approach 1:
The patent implements pre-fetching of compressed data for sub-lines when retrieving compressed data for another sub-line within the same LLC line. This preliminary action reduces future access latency by loading data into the LLC before it is needed, resolving the contradiction between maintaining memory bandwidth protection and reducing access latency.
3Productivity
If multiple sub-lines are read from LLC in combination, then memory bandwidth utilization is improved, but control complexity increases
Solution Approach 1:
The patent enables the CMC to automatically manage the compression and retrieval processes across multiple sub-lines without requiring external intervention. The CMC independently handles pre-fetching, compression, and coordinated retrieval operations, improving memory bandwidth utilization while keeping the control mechanism manageable through self-service automation.
Data Source
AI summary
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.