Cascaded Multilevel Inverter Duty Cycle Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional fundamental frequency modulation (FFM) in cascaded multilevel inverters (CMIs) leads to unequal active/reactive power distribution among H-bridge modules due to unequal pulse-widths of output voltages, causing DC capacitor current and voltage ripples, which results in excessive voltage stress on insulated-gate bipolar transistors (IGBTs) and necessitates over-sized capacitors, contradicting modular design principles.
Innovation Solution
A controller is used to optimize FFM by transferring a portion of the duty cycle from a first H-bridge module with a greater duty cycle to a second H-bridge module with a lesser duty cycle, reducing activity in the first module and increasing it in the second during specific periods, thereby equalizing DC capacitor currents and voltage ripples across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional fundamental frequency modulation is used in CMIs, then switching loss is reduced, but unequal power distribution among H-bridge modules occurs due to unequal pulse-widths
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the duty cycles of H-bridge modules based on real-time power distribution requirements. The controller modifies the duty cycle parameters to ensure equal active and reactive power sharing among modules, resolving the unequal power distribution issue while maintaining the low switching loss benefits of fundamental frequency modulation
2Device complexity
If traditional FFM is used, then modulation simplicity is maintained, but DC capacitor current and voltage ripples increase due to unequal duty cycles
Solution Approach 1:
The patent implements feedback control by continuously monitoring the active and reactive power output of each H-bridge module and adjusting their duty cycles accordingly. This feedback mechanism equalizes the DC capacitor currents and voltage ripples across all modules while maintaining the simplicity of fundamental frequency modulation, improving DC capacitor reliability without significantly increasing system complexity
3Object-affected harmful factors
If DC-link capacitance is increased to withstand higher capacitor currents, then voltage stress on IGBTs is reduced, but cost increases and modular design principles are violated
Solution Approach 1:
The patent uses parameter changes to dynamically balance the duty cycles of H-bridge modules, which equalizes the DC capacitor currents and voltage ripples. This approach reduces the peak current stress on IGBTs without requiring increased DC-link capacitance, thereby maintaining cost-effectiveness and adhering to modular design principles where all modules use identical capacitor specifications
Data Source
AI summary
A system and a method for optimizing fundamental frequency modulation in a cascaded multilevel inverter (CMI) are provided. The CMI includes at least a first H-bridge module and a second H-bridge module connected in series with the first H-bridge module. The first H-bridge module is operated according to a first duty cycle and the second H-bridge module is operated according to a second duty cycle. The first duty cycle is greater than the second duty cycle. The first and second H-bridge modules are controlled utilizing fundamental frequency modulation. A portion of the first duty cycle is transferred to the second duty cycle thereby optimizing fundamental frequency modulation by at least improving power sharing between the first and second H-bridge modules and improving equalization of DC capacitor currents and voltage ripples while maintaining the same fundamental modulation to the output voltage waveform.