CMIS Strained Silicon Transistor Parasitic Resistance

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Solution Overview

Problem

The existing strained silicon techniques for CMIS devices face challenges in maintaining the operating characteristics of n-channel field effect transistors while degrading those of p-channel transistors, particularly due to issues with heat treatment temperatures and carbon concentration optimization in Si:C source/drain formation.

Innovation Solution

A semiconductor device design where an n-channel field effect transistor with a Si:C layer is formed using a second n-type impurity diffusion layer positioned deeper than the first, and a Si:C layer with maximum carbon concentration is created through ion-implantation and subsequent heat treatment, optimizing strain and parasitic resistance without degrading p-channel performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If carbon concentration is increased to enhance strain effect, then mobility of electrons is improved, but parasitic resistance increases

Engineering Contradiction:
Improvemobility of electronsVSAvoidparasitic resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The carbon concentration in the Si:C layer is precisely controlled and optimized to achieve the desired strain effect. By adjusting the carbon concentration parameter within an optimal range, the patent achieves maximum electron mobility improvement while keeping parasitic resistance at acceptable levels. The Si:C layer is formed with a specific carbon content that provides sufficient strain without excessive resistance penalty

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of varying carbon concentration uniformly throughout the source/drain region, the patent positions the Si:C layer at a specific depth dimension within the second n-type impurity diffusion layer. This depth positioning creates a three-dimensional distribution where strain is applied where most beneficial to the channel while minimizing the overall carbon content to reduce parasitic resistance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the operating characteristics of n-channel transistors without compromising the performance of p-channel transistors, achieving enhanced mobility and strain optimization in CMIS devices.

Implementation Method 1

a strained silicon (Si) technique. This is a technique capable of achieving the improvement in the carrier mobility by applying a strain to a silicon layer. That is, if the silicon crystal lattice in a channel is strained by applying a stress to the channel, the symmetry of the band structure of the isotropic silicon crystal is broken, resulting in splitting in energy levels.

Methodology Applied
Scientific EffectStrain: Deformation

Implementation Method 2

a method of forming the Si:C layer by ion-implanting carbon in forming an impurity diffusion layer constituting the source/drain

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 3

by applying a heat treatment to the substrate, the n-type impurities within the first and second n-type impurity diffusion layers and the p-type impurities within the first and second p-type impurity diffusion layers are activated

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Data Source

PatentUS8343827B2Semiconductor device and manufacturing method of the same
Publication Date: 2013.01.01 RENESAS ELECTRONICS CORP
  • US8343827B2 patent drawing
  • US8343827B2 patent drawing
  • US8343827B2 patent drawing

AI summary

In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.