CML Buffer Active Inductor Tuning for Wideband Frequency Response
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Solution Overview
Problem
Common mode logic (CML) buffer circuits face challenges in achieving adjustable frequency responses and effective bandwidth, particularly in high-speed applications like programmable logic devices (PLDs), where existing solutions either consume significant power or result in noise issues due to large passive inductors and resistors.
Innovation Solution
A CML buffer circuit utilizing a pair of MOS transistors configured as active inductors, with adjustment circuits that modify resistance and capacitance values in response to a control signal, allowing for dynamic adjustment of the input-output transfer function and effective impedance to optimize frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive inductors and resistors are used to adjust frequency response in CML buffer circuits, then the frequency response can be adjusted, but noise and power consumption increase significantly
Solution Approach 1:
The patent replaces passive inductor-resistor circuits with an active circuit implementation using MOS transistors (specifically transistor 206) configured to provide inductive peaking functionality. This substitution eliminates the need for physical passive inductors and resistors, thereby reducing noise generation and power consumption while maintaining frequency response adjustability through control signals.
Solution Approach 2:
The patent enables dynamic adjustment of the frequency response by changing the effective impedance of the active inductor through control signals. The input-output transfer function can be varied by adjusting parameters such as the gate voltage of transistor 206, allowing the pole frequency to be shifted without requiring physical component changes, thus maintaining adaptability while minimizing noise and power consumption.
2Adaptability or versatility
If passive inductors are used in CML buffer circuits, then frequency response adjustment is possible, but the circuit area and device complexity increase
Solution Approach 1:
The patent substitutes physical passive inductor components with an active transistor-based implementation. Transistor 206 is configured to emulate inductive behavior through its impedance characteristics, eliminating the need for large-area passive inductor components while achieving the same frequency response adjustment functionality through electrical control.
Solution Approach 2:
The active inductor implementation using transistor 206 serves multiple functions: it provides inductive peaking for frequency response adjustment, acts as an impedance transformation element, and enables dynamic control through gate voltage adjustment. This multi-functionality consolidates what would otherwise require separate passive components into a single active device, reducing overall circuit area.
3Speed
If the bandwidth of CML buffer circuits is increased, then high-speed signal processing is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the frequency response characteristics through control signals that adjust the effective impedance of the active inductor (transistor 206). This allows the bandwidth to be adjusted dynamically according to operational requirements rather than being fixed by passive components, enabling optimization of power consumption by matching the bandwidth to the actual signal processing needs.
Solution Approach 2:
The patent enables adjustment of the pole frequency and bandwidth by changing the electrical parameters of the active inductor circuit. By varying the gate voltage or control signal parameters, the effective inductance and resistance are modified, allowing bandwidth optimization without the proportional power consumption increase that would result from using larger passive inductors or resistors.
Data Source
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AI summary
A common mode logic buffer device includes a current source (112) configured to provide a source current. An input stage includes a first MOS transistor pair (110) configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair (106) configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit (104, 108) is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair (106).