Current-Mode Logic Buffer Phasing for Lower-EMI Clock Signals
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Solution Overview
Problem
High-speed transmission interfaces face significant electromagnetic interference issues due to high data transmission rates, which existing methods like adding metal interfaces or reducing amplifier slew rates cannot effectively mitigate without generating harmonics that damage electronic circuits.
Innovation Solution
A current mode logic buffer device with multiple sets of current mode logic buffers that generate clock signals with increased rising and falling times, effectively producing a sine wave output to reduce harmonic energy and mitigate electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data transmission rate is increased for high-speed transmission interface, then the transmission speed is improved, but electromagnetic interference is generated
Solution Approach 1:
The patent uses multiple current mode logic buffers operating at different phases to generate clock signals that are combined to form a full clock signal. This periodic action with phase distribution reduces the peak electromagnetic interference while maintaining high data transmission rates.
Solution Approach 2:
The patent changes the operational parameters of the clock signal generation by using multiple buffers with different phase delays (time differences) to generate clock signals that when combined produce a sine-wave-like full clock signal, reducing harmonic content and electromagnetic interference.
2Object-affected harmful factors
If a metal interface is added to mitigate electromagnetic interference, then electromagnetic interference is reduced, but the cost increases
Solution Approach 1:
Instead of adding physical metal interfaces, the patent changes the electrical parameters of the clock signal generation process by using multiple current mode logic buffers with phase delays to create a full clock signal with reduced harmonic content, thereby reducing electromagnetic interference without increasing manufacturing cost.
3Object-affected harmful factors
If the slew rate of the amplifier output is reduced to mitigate electromagnetic interference, then electromagnetic interference is reduced and energy is reduced in some frequency bands, but harmonics are generated that cause damage to electronic circuits
Solution Approach 1:
The patent employs multiple current mode logic buffers operating in a periodic sequence with phase delays to generate clock signals that combine to form a full clock signal. This periodic action with distributed phases produces a sine-wave-like output that reduces both electromagnetic interference and harmful harmonics simultaneously.
Solution Approach 2:
The patent merges the outputs of multiple current mode logic buffers with different phase delays to create a full clock signal. This combining of multiple phase-shifted clock signals produces a sine-wave-like waveform that reduces harmonic content and electromagnetic interference without damaging electronic circuits.
Data Source
AI summary
A current mode logic buffer device for suppressing electromagnetic interference includes two output ports and three or more sets of current mode logic buffers. First, second, and third current mode logic buffers respectively generate first, second, and third clock signals in response to first, second, and third differential input signals. The second differential input signal is delayed by a time difference from the first differential input signal, and the third differential input signal is delayed by the time difference from the second differential input signal. The output ports receive the first clock signal, the second clock signal, and the third clock signal, and output a full clock signal. A signal generating method for suppressing electromagnetic interference is also provided.