Source-Synchronous Chip Interface With Fast Bias Turn-On and CML Clocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Achieving effective power reduction in mobile system link architectures is challenging due to inconsistent power consumption and latency, particularly in low-power systems, and architecting power modes to achieve bandwidth agility and lower total power involves additional delay and complexity.
Innovation Solution
The implementation of a low-power, high-performance source-synchronous chip interface with a fast turn-on bias circuit, current mode logic (CML) clock buffers, and digitally controlled delay lines (DCDLs) to rapidly transition between power states, reducing power supply ringing and jitter, while maintaining high signaling rates and immunity to power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional low-power interfaces use circuits with turn-on or clock phase lock acquisition, then power consumption is reduced, but latency increases and power consumption becomes inconsistent with dynamic requirements
Solution Approach 1:
The patent implements dynamic power management by enabling the interface circuit to rapidly transition between different power states (zero power to full data rate) based on operational requirements. The source-synchronous signaling with fast turn-on bias circuit allows the system to dynamically adjust power consumption without incurring significant latency penalties, as the circuit can activate in less than 8 nanoseconds from a zero-power state.
2Loss of energy
If architecting power modes to achieve bandwidth agility and lower total power, then power efficiency improves, but additional delay and complexity are introduced
Solution Approach 1:
The patent extracts the clock recovery function from the traditional clock distribution architecture by implementing source-synchronous signaling where timing information is embedded within the data signal itself. This eliminates the need for separate clock buffers and phase-locked loops, thereby reducing device complexity while maintaining the ability to achieve bandwidth agility and power efficiency through rapid power state transitions.
3Loss of time
If rapid transition from zero power to full data rate is implemented, then latency is reduced, but power supply ringing and jitter may increase
Solution Approach 1:
The patent applies preliminary action by pre-charging bias circuits and preparing signal paths before full-power operation is required. The fast turn-on bias circuit pre-establishes the necessary voltage levels and signal conditions, enabling the interface to transition to full data rate in less than 8 nanoseconds without causing significant power supply ringing or jitter. This pre-preparation eliminates the need for gradual ramp-up that would otherwise be required to avoid harmful power supply effects.
Data Source
AI summary
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.