CML-to-CMOS Clock Conversion Without Amplifier Delay
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Solution Overview
Problem
Conventional CML to CMOS clock signal conversion circuits experience significant delay, which exceeds the clock cycle in high-speed parallel-serial conversion processes, necessitating a reduction in delay time to maintain operational efficiency.
Innovation Solution
The proposed CML to CMOS conversion circuit omits the amplifier and incorporates a parallel resistor connection between the input and output terminals of an inverter, utilizing NMOS and PMOS transistors, to reduce delay time by expanding the bandwidth of the inverter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the conventional CML to CMOS conversion circuit configuration (including amplifier and two inverters) is used, then the circuit maintains functional effectiveness, but the delay time is excessive (64 ps) for high-speed parallel-serial conversion
Solution Approach 1:
The patent removes the amplifier from the conventional CML to CMOS conversion circuit, extracting only the essential components (differential units and inverter) needed for signal conversion. This extraction eliminates the delay contribution of the amplifier while maintaining the core conversion functionality, reducing total delay from 64 ps to 34 ps.
Solution Approach 2:
The patent inverts the conventional approach by connecting the output of the differential unit directly to the input of the inverter, rather than passing through an amplifier first. This inversion of the signal path removes the amplification stage entirely, achieving faster conversion while the resistor parallel connection to the inverter compensates for any gain loss.
2Loss of time
If the amplifier is removed from the conversion circuit, then the delay time is reduced, but the signal amplification function must be maintained through alternative means
Solution Approach 1:
The patent changes the operating parameters of the inverter by adding a resistor in parallel with its output. This parameter modification allows the inverter to provide both signal inversion and amplification functions simultaneously, compensating for the removed amplifier while maintaining fast response time. The resistor value is optimized to achieve the desired balance between delay reduction and signal drive capability.
Data Source
AI summary
The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.