CML to CMOS Converter Using Pulse Current Compensation
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Solution Overview
Problem
Current CML to CMOS converters face inefficiencies due to high power consumption and increased area occupancy on semiconductor dies, primarily because they rely on larger capacitors to filter current spikes and maintain a consistent midpoint voltage, which reduces efficiency and increases area usage.
Innovation Solution
A pulse current compensation circuit using a differential transistor pair, current mirrors, and a transistor to dynamically adjust current sinks based on input differential signals, reducing the need for large capacitors and minimizing power consumption by shielding the reference circuit from current changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If larger capacitors are used to filter current spikes and shield the reference circuit, then the midpoint voltage consistency is improved, but the area occupied on the semiconductor die increases
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary component between the CML signal processing circuit and the reference circuit. This buffer circuit absorbs current spikes and isolates the reference circuit from voltage variations, thereby maintaining midpoint voltage consistency without requiring large capacitors. The buffer circuit acts as a mediator that protects the reference circuit while occupying minimal area compared to large filtering capacitors.
2Stability of the object's composition
If higher currents are forced through the reference circuit to reduce the impact of current spikes, then the midpoint voltage stability is improved, but the power consumption increases
Solution Approach 1:
The buffer circuit serves as a protective intermediary that shields the reference circuit from current spikes generated by the CML signal processing circuit. By placing this buffer between the two circuits, the reference circuit operates with stable, low current while the buffer absorbs the high current spikes. This eliminates the need to force high currents through the reference circuit to achieve stability, thereby significantly reducing power consumption.
Solution Approach 2:
The buffer circuit provides beforehand cushioning by being positioned upstream of the reference circuit to absorb and dampen current spikes before they can reach and disturb the reference circuit. This preemptive protection allows the reference circuit to maintain stable midpoint voltage with minimal current consumption, as the cushioning effect is already in place to handle any current variations.
3Speed
If CML signal processing circuits are used to achieve fast voltage transitions, then the data transmission speed is improved, but the standby power consumption and area occupancy increase
Solution Approach 1:
The patent merges the advantages of both CML and CMOS technologies by creating a hybrid architecture. The CML signal processing circuit handles high-speed signal reception and initial processing, while the CMOS logic circuit performs subsequent processing at lower speeds. The buffer circuit couples these two stages, allowing the system to achieve fast voltage transitions where needed (in the CML stage) while minimizing standby power consumption in the CMOS stage, thereby combining the speed benefits of CML with the power efficiency of CMOS.
Data Source
AI summary
A CML to CMOS signal conversion system includes a CML/CMOS converter coupled to a resistor, which is further coupled to a current compensation circuit at a reference node. The CML/CMOS converter receives a differential signal and applies a first or a second current to the reference node through the resistor. The current compensation circuit comprises a differential transistor pair coupled to a current source, a transistor, and a first, a second, and a third current mirror. The differential transistor pair receives the differential signal and has a pair of output terminals. The first current mirror is coupled to the output terminals. The third current mirror is coupled to the reference node. The first and third current mirror are coupled together by the transistor and sink the first current. The second current mirror is coupled to the output terminals and the reference node and sinks the second current.